Zero-delay buffers (ZDB) provide a synchronous copy (no propagation delay) of the input clock at the outputs, usually without frequency translation. The Renesas ZDBs are PLL-based devices that regenerate the input clock signal with fanout to drive multiple loads offering various signal levels, including LVPECL, LVDS, HCSL, CML, HSTL, SSTL or LVCMOS. ZDBs are ideal for applications requiring synchronized clocking for FPGAs, CPUs, logic and synchronous memory.

Most zero-delay buffers allow the delay through the device to be adjusted through an external feedback path. This allows precise control of the timing of the clock signals to the loads. Simple frequency translation is possible with a ZDB when a single divider is used for all outputs, including feedback output, to maintain clock synchronization.

Hint: If more than one unique output frequency is required (eg. 100MHz and 125Mhz), make use of the “Output Banks” parametric selector. Each bank corresponds to a unique output frequency.

Download: Clock Distribution Overview (PDF | English, 日本語)

Industry-leading Zero-delay Buffer Solutions

The Renesas zero-delay buffer (ZDB) IC families are available with a wide range of options and features. Differential outputs such as LVPECL, LVDS, HCSL, CML, HSTL, SSTL, as well as selectable outputs, are supported for output frequencies up to 3.2 GHz and single-ended LVCMOS outputs for frequencies up to 350 MHz. In addition, Renesas' PLL portfolio has devices supporting supply voltages from 1.2 V up to 3.3 V and that are available in the commercial and industrial temperature ranges.

Using a Renesas PLL product has many benefits. Reducing the number of quartz crystals on a board improves reliability because crystals are highly susceptible to shock and vibration. Using a clock signal generator also reduces a customer's board cost and space, bill of materials (BOM) and inventory levels by replacing multiple crystals and oscillators with one device. They are ideal for use in a large variety of systems, from personal computers to consumer electronics or industrial systems, as well as high-performance networking and communications systems.

Selecting a Zero-delay Buffer (ZDB)

There are many important factors when choosing a ZDB for a particular application. The following parameters will give users a basic starting point to narrow down the potential solutions:

  • # of outputs: choose a ZDB with enough outputs to simplify your clock tree. Fewer components simplifies the design and procurement process for faster time to market, and can even improve reliability for better production yields. Renesas offers some of the industry’s most integrated solutions for highly-complex systems, along with right-sized solutions for those that fall in between.
  • output type: this is the signalling type of the output that is required of the zero-delay buffer. Renesas offers LVPECL, LVDS, HCSL, CML, HSTL, SSTL or LVCMOS.
  • input / output frequency range: the valid range of input and output frequencies. Renesas offers zero-delay buffers to address the frequency needs of all popular applications.
  • core voltage: the supply voltage used to power the ZDB. This is typically defined by the power rails available in the system, and often has implications on voltage levels of the output. Renesas zero-delay buffers are offered in voltages from 3.3 V down to 1.5V.

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