The 8T33FS6111 is a bipolar monolithic differential clock fanout buffer. Designed for most demanding clock distribution systems, the 8T33FS6111 supports various applications that require distribution of precisely aligned differential clock signals. Using SiGe:C technology and a fully differential architecture, the device offers very low skew outputs and superior digital signal characteristics. Target applications for this clock driver is high performance clock distribution in computing, networking and telecommunication systems.
The 8T33FS6111 is designed for low skew clock distribution systems and supports clock frequencies up to 2.7GHz. The device accepts two clock sources. The CLKA input can be driven by LVPECL compatible signals, the CLKB input accepts HSTL or LVPECL compatible signals. The selected input signal is distributed to 10 identical, LVPECL outputs. If VBB is connected to the CLKA input and bypassed to GND by a 10nF capacitor, the 8T33FS6111 can be driven by single-ended LVPECL signals utilizing the VBB bias voltage output.
In order to meet the tight skew specification of the device, both outputs of a differential output pair should be terminated, even if only one output is used. In the case where not all ten outputs are used, the output pairs on the same package side as the parts being used on that side should be terminated. The 8T33FS6111 can be operated from a single 3.3V or 2.5V supply.


  • 1:10 differential clock distribution
  • 28ps typical output skew
  • Fully differential architecture from input to all outputs
  • SiGe:C technology supports near-zero output skew
  • Supports DC to 2.7GHz operation of clock or data signals
  • LVPECL compatible differential clock outputs
  • LVPECL/HSTL compatible differential clock inputs
  • Single 3.3V or 2.5V supply
  • Standard 32-Lead VFQFN package
  • Standard 32-lead LQFP package
  • Standard 32-lead TQFP package with EPAD
  • -40°C to 85°C ambient operating temperature

Product Options

Orderable Part ID Part Status Pkg. Type Lead Count (#) Temp. Grade Pb (Lead) Free Carrier Type Buy Sample
Active PTQFP 32 I Yes Tray
Active PTQFP 32 I Yes Reel

Documentation & Downloads

Title Other Languages Type Format File Size Date
Datasheets & Errata
8T33FS6111 Datasheet Datasheet PDF 904 KB
Application Notes & White Papers
AN-828 Termination - LVPECL Application Note PDF 322 KB
AN-844 Termination - AC Coupling Clock Receivers Application Note PDF 170 KB
AN-842 Thermal Considerations in Package Design and Selection Application Note PDF 495 KB
AN-840 Jitter Specifications for Timing Signals Application Note PDF 442 KB
AN-833 Differential Input Self Oscillation Prevention Application Note PDF 180 KB
AN-834 Hot-Swap Recommendations Application Note PDF 153 KB
AN-836 Differential Input to Accept Single-ended Levels Application Note PDF 120 KB
AN-835 Differential Input with VCMR being VIH Referenced Application Note PDF 160 KB
AN-827 Application Relevance of Clock Jitter Application Note PDF 1.15 MB
AN-815 Understanding Jitter Units Application Note PDF 565 KB
AN-805 Recommended Ferrite Beads Application Note PDF 121 KB
PCN# : A2003-01 Add Greatek Taiwan as an Alternate Assembly Location on Select Packages Product Change Notice PDF 113 KB
PCN# : A1904-01 Add Greatek, Taiwan as an Alternate Assembly Facility Product Change Notice PDF 983 KB
PDN# : CQ-18-04 PRODUCT DISCONTINUANCE NOTICE Product Discontinuation Notice PDF 550 KB
PCN# : A1709-02 Add alternate assembly at OSET and Convert to Copper Wire Product Change Notice PDF 35 KB
PCN# : A1611-02 Add JCET China as Alternate Assembly and Change of Material Set at Alternate Assembly Location Product Change Notice PDF 583 KB
PCN# : A1602-01(R1) Add Greatek Taiwan as Alternate Assembly Product Change Notice PDF 611 KB
PCN# : A1602-01 Add Greatek Taiwan as Alternate Assembly Product Change Notice PDF 611 KB
PCN# : A1511-01(R1) Add SPEL India as Alternate Assembly Location Product Change Notice PDF 596 KB
PCN# : A1511-01 Add SPEL India as Alternate Assembly Location Product Change Notice PDF 544 KB
Clock Distribution Overview 日本語 Overview PDF 217 KB
IDT Clock Generation Overview 日本語 Overview PDF 1.83 MB