The IDT6P61033 is an 8-output very low power buffer for 100MHz PCIe Gen1, Gen2 and Gen3 applications with integrated output terminations providing Zo=100Ω. The device has 8 output enables for clock management, and 3 selectable SMBus addresses.
Features
DIF cycle-to-cycle jitter <50ps
DIF output-to-output skew <50ps
DIF phase jitter is PCIe Gen1-2-3 compliant
Very low additive phase jitter in bypass mode
Integrated terminations provide 100Ω differential Zo reduced component count and board space
1.8V operation; minimal power consumption
Outputs can optionally be supplied from any voltage between 1.05 and 1.8V; maximum power savings
OE# pins; support DIF power management
HCSL compatible differential input; can be driven by common clock sources
LP-HCSL differential clock outputs; reduced power and board space
Programmable Slew rate for each output; allows tuning for various line lengths
Programmable output amplitude; allows tuning for various application environments
Pin/software selectable PLL bandwidth and PLL Bypass; minimize phase jitter for each application
Outputs blocked until PLL is locked; clean system start-up
Software selectable 50MHz or 125MHz PLL operation; useful for Ethernet applications
Configuration can be accomplished with strapping pins; SMBus interface not required for device control
3.3V tolerant SMBus interface works with legacycontrollers
Space saving 48-pin 6x6mm VFQFPN; minimal board space
Selectable SMBus addresses; multiple devices can easily share an SMBus segment
Comparison
Applications
Documentation
Design & Development
Models
ECAD Models
Schematic symbols, PCB footprints, and 3D CAD models from SamacSys can be found by clicking on products in the Product Options table. If a symbol or model isn't available, it can be requested directly from the website.