Overview

The 9FGL839 is an 8-output differential synthesizer for PCI Express Gen 1, Gen 2, and Gen 3 applications. It has integrated terminations providing direct connection to 100Ω transmission lines and saving 32 resistors compared to standard HCSL outputs. The 9FGL839 supports common, data, and Separate Reference no-Spread (SRnS) PCIe clock architectures.

9FGL839 Block Diagram
9FGL839 Pinout
9FGL839 Block Diagram
9FGL839 Pinout
  • Integrated terminations; save 32 resistors compared to standard HCSL outputs
  • LP-HCSL outputs; support separate VDDIO rail and 130mW typical power consumption
  • 8 OE# pins; hardware control of each output
  • 25MHz crystal input; exact synthesis
  • 100MHz operation; supports PCIe and SATA applications
  • VDDIO; allows outputs to run from lower voltage rail to save power
  • OE# pins have 1.5V high input threshold; direct interface to 1.8V to 3.3V systems
  • < 130mW power consumption (typical)
  • Cycle-to-Cycle jitter < 50ps
  • Output-to-Output skew < 100ps
  • PCIe Gen 2 phase jitter < 3.0ps RMS
  • PCIe Gen 3 phase jitter < 1.0ps RMS
  • PCIe Gen 3 SRnS clock phase jitter < 0.7ps RMS

Documentation

Design & Development

ECAD Models

Schematic symbols, PCB footprints, and 3D CAD models from SamacSys can be found by clicking on products in the Product Options table. If a symbol or model isn't available, it can be requested directly from the website.

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Diagram of ECAD Models

Product Options

    Processing table
    Pkg. Type
    Lead Count (#)
    Temp. Grade
    Pb (Lead) Free
    Carrier Type
    Buy / Sample
    Part Number
    9FGL839AKILF
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    view_in_ar
    		VFQFPN 48 I Yes Tray
    9FGL839AKILFT
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    memory
    view_in_ar
    		VFQFPN 48 I Yes Reel
    9FGL839AKLF
    circleObsolete
    memory
    view_in_ar
    		VFQFPN 48 C Yes Tray
    9FGL839AKLFT
    circleObsolete
    memory
    view_in_ar
    		VFQFPN 48 C Yes Reel
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    PCIe Clocking Architectures (Common and Separate)

    This is the first video in our PCIe series. In this video, we define PCIe architectures, focusing on common and separate clock architectures. Watch the rest of the video series below where Ron will cover the impact of different timing architectures.

    Watch the Video Series Below

    Video List
    PCIe Clocking Architectures (Common and Separate)
    PCIe Common Clock Architecture and its Impact on Clocking
    PCIe Separate Reference without Spread Clock Architecture
    PCIe Separate Reference Clock With Independent Spread (SRIS) Architecture Overview