This FET has the over temperature shut-down capability sensing to the junction temperature. This FET has the built-in over temperature shut-down circuit in the gate area. And this circuit operation to shut-down the gate voltage in case of high junction temperature like applying over power consumption, over current etc.

Features

  • Logic level operation (4 to 6 V Gate drive)
  • High endurance capability against to the short circuit
  • Built-in the over temperature shut-down circuit
  • Latch type shut-down operation (Need 0 voltage recovery)

Product Options

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Documentation & Downloads

Title Other Languages Type Format File Size Date
Datasheets & Errata
HAF2011(L) HAF2011(S) Datasheet 日本語 Datasheet PDF 130 KB
Application Notes & White Papers
Power MOS FET APPLICATION NOTE 日本語 Application Note PDF 814 KB
PCNs & PDNs
Unification of a JEDEC tray and a embossed carrier tape for LQFP package (Additional Information & Correction) 日本語 Product Change Notice PDF 4.86 MB
Unification of a JEDEC tray and a embossed carrier tape for LQFP package 日本語 Product Change Notice PDF 3.74 MB
Unification of a JEDEC tray and a embossed carrier tape for LQFP package 日本語 Product Change Notice PDF 1.46 MB
Other
Product Scout Automotive Brochure PDF 3.25 MB
PowerMOSFET & IPD Brochure PDF 2.24 MB
Power supply system Brochure PDF 5.75 MB
Renesas Discrete Transistor / Diode / Triac / Thyristor General Catalog Brochure PDF 7.66 MB
Renesas Semiconductor Lead-Free Packages Brochure PDF 1.32 MB