Overview

Description

Dual DDR zero delay buffer

Features

  • High performance, low jitter zero delay buffer
  • I2C for functional and output control
  • Dual bank 1-6 differential clock distribution
  • 2 separate feedback in & out for input to output
  • Synchronization for each bank
  • Supports up to 4 DDR DIMMs
  • Supports up to 533MHz (DDRII 1066)

Comparison

Applications

Documentation

Design & Development

Models