The IDT9170B generates an output clock which is synchronized to a given continuous input clock with zero delay (±1ns at 5 V VDD). Using IDT's proprietary phase-locked loop (PLL) analog CMOS technology, the IDT9170B is useful for regenerating clocks in high speed systems where skew is a major concern. By the use of the two select pins, multiples or divisions of the input clock can be generated with zero delay (see Tables 2 and 3). The standard versions produce two outputs, where CLK2 is always a divide by two version of CLK1. The IDT9170B is also useful to recover poor duty cycle clocks. A 50 MHz signal with a 20/80% duty cycle, for example, can be regenerated to the 48/52% typical of the part. The IDT9170B allows the user to control the PLL feedback, making it possible, with an additional 74F240 octal buffer (or other such device that offers controlled skew outputs), to synchronize up to 8 output clocks with zero delay compared to the input. Application notes for the IDT9170B are available. Please consult IDT.


  • On-chip Phase-Locked Loop for clocks synchronization.
  • Synchronizes frequencies up to 107 MHz (output) @ 5.0 V
  • ±1ns skew (max) between input & output clocks @ 5.0 V
  • Can recover poor duty cycle clocks
  • CLK1 to CLK2 skew controlled to within ±1ns @ 5.0 V
  • 3.0 - 5.5 V supply range
  • Low power CMOS technology
  • Small 8-pin DIP or SOIC package
  • On chip loop filter
  • IDT9170B-01 for output clocks 20-107 MHz @ 5.0 V, 20 - 66.7 MHz @ 3.3 V
  • IDT9170B-02 for output clocks 5-26.75 MHz @ 5.0 V, 5 - 16.7 MHz @ 3.3 V

Product Options

Part Number Part Status Pkg. Type Lead Count (#) Temp. Grade Pb (Lead) Free Carrier Type Buy Sample
Obsolete SOIC 8 C Yes Tube
Obsolete SOIC 8 C Yes Reel


Title language Type Format File Size Date
Datasheets & Errata
9170B Datasheet Datasheet PDF 376 KB
Application Notes & White Papers
AN-828 Termination - LVPECL Application Note PDF 322 KB
AN-831 The Crystal Load curve Application Note PDF 395 KB
AN-844 Termination - AC Coupling Clock Receivers Application Note PDF 170 KB
AN-845 Termination - LVCMOS Application Note PDF 146 KB
AN-842 Thermal Considerations in Package Design and Selection Application Note PDF 495 KB
AN-840 Jitter Specifications for Timing Signals Application Note PDF 442 KB
AN-838 Peak-to-Peak Jitter Calculations Application Note PDF 115 KB
AN-839 RMS Phase Jitter Application Note PDF 233 KB
AN-832 Timing Budget and Accuracy Application Note PDF 131 KB
AN-834 Hot-Swap Recommendations Application Note PDF 153 KB
AN-830 Quartz Crystal Drive Level Application Note PDF 143 KB
AN-815 Understanding Jitter Units Application Note PDF 565 KB
AN-827 Application Relevance of Clock Jitter Application Note PDF 1.15 MB
AN-802 Crystal-Measuring Oscillator Negative Resistance Application Note PDF 136 KB
AN-801 Crystal-High Drive Level Application Note PDF 202 KB
AN-805 Recommended Ferrite Beads Application Note PDF 121 KB
AN-806 Power Supply Noise Rejection Application Note PDF 438 KB
AN-803 Crystal Timing Budget and Accuracy for Renesas Timing Clock Products Application Note PDF 108 KB
PCN# : TB1303-02 Change of Tape & Reel Packing Method for Selective Products Product Change Notice PDF 361 KB
PCN# : A1208-01R1 Gold to Copper Wire Product Change Notice PDF 254 KB
PDN# : K-13-01R2 PRODUCT DISCONTINUANCE NOTICE Product Discontinuation Notice PDF 125 KB
PDN# : K-13-01R1 PRODUCT DISCONTINUANCE NOTICE Product Discontinuation Notice PDF 125 KB
PDN# : K-13-01 PRODUCT DISCONTINUANCE NOTICE Product Discontinuation Notice PDF 122 KB