Overview

The 5T9302 2.5V differential clock buffer is a user-selectable differential input to two LVDS outputs. The fanout from a differential input to two LVDS outputs reduces loading on the preceding driver and provides an efficient clock distribution network. The 5T9302 can act as a translator from a differential HSTL, eHSTL, LVEPECL (2.5V), LVPECL (3.3V), CML, or LVDS input to LVDS outputs. A single-ended 3.3V / 2.5V LVTTL input can also be used to translate to LVDS outputs. The redundant input capability allows for an asynchronous change-over from a primary clock source to a secondary clock source. Selectable reference inputs are controlled by SEL. The 5T9302 outputs can be asynchronously enabled/disabled. When disabled, the outputs will drive to the value selected by the GL pin. Multiple power and grounds reduce noise.

5T9302 - Block Diagram
5T9302 - Pinout
5T9302 - Block Diagram
5T9302 - Pinout
  • Guaranteed low skew: 5ps (typical)
  • Very low duty cycle distortion: 20ps (typical)
  • High speed propagation delay: 1.35ns (typical)
  • Up to 450MHz operation
  • Selectable inputs
  • Hot insertable and over-voltage tolerant inputs
  • 3.3V/2.5V LVTTL, HSTL eHSTL, LVEPECL (2.5V), LVPECL (3.3V), CML or LVDS input interface
  • Selectable differential inputs to two LVDS outputs
  • Power-down mode
  • 2.5V VDD
  • 0°C to 70°C ambient operating temperature
  • Available in TSSOP package

Documentation

Design & Development

ECAD Models

Schematic symbols, PCB footprints, and 3D CAD models from SamacSys can be found by clicking on products in the Product Options table. If a symbol or model isn't available, it can be requested directly from the website.

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Product Options

    Processing table
    Pkg. Type
    Lead Count (#)
    Temp. Grade
    Pb (Lead) Free
    Carrier Type
    Buy / Sample
    Part Number
    5T9302EJGI
    circleObsolete
    memory
    view_in_ar
    		TSSOP 20 I Yes Tube
    5T9302EJGI8
    circleObsolete
    memory
    view_in_ar
    		TSSOP 20 I Yes Reel
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