-- generated by newgenasym Wed Jun 07 14:31:05 2006

library ieee;
use     ieee.std_logic_1164.all;
use     work.all;
entity ics9db801 is
    port (    
	\bypass#/pll\: IN     STD_LOGIC;    
	DIF_0:     INOUT  STD_LOGIC;    
	\dif_0#\:  INOUT  STD_LOGIC;    
	DIF_1:     OUT    STD_LOGIC;    
	\dif_1#\:  OUT    STD_LOGIC;    
	DIF_2:     OUT    STD_LOGIC;    
	\dif_2#\:  OUT    STD_LOGIC;    
	DIF_3:     INOUT  STD_LOGIC;    
	\dif_3#\:  INOUT  STD_LOGIC;    
	DIF_4:     INOUT  STD_LOGIC;    
	\dif_4#\:  INOUT  STD_LOGIC;    
	DIF_5:     OUT    STD_LOGIC;    
	\dif_5#\:  OUT    STD_LOGIC;    
	DIF_6:     OUT    STD_LOGIC;    
	\dif_6#\:  OUT    STD_LOGIC;    
	DIF_7:     INOUT  STD_LOGIC;    
	\dif_7#\:  INOUT  STD_LOGIC;    
	GND01:     INOUT  STD_LOGIC;    
	GND02:     INOUT  STD_LOGIC;    
	GND03:     INOUT  STD_LOGIC;    
	GND04:     INOUT  STD_LOGIC;    
	GND05:     INOUT  STD_LOGIC;    
	GNDA:      IN     STD_LOGIC;    
	\high_bw#\: IN     STD_LOGIC;    
	IREF:      OUT    STD_LOGIC;    
	LOCK:      INOUT  STD_LOGIC;    
	\oe0#\:    INOUT  STD_LOGIC;    
	\oe1#\:    IN     STD_LOGIC;    
	\oe2#\:    INOUT  STD_LOGIC;    
	\oe3#\:    INOUT  STD_LOGIC;    
	\oe4#\:    INOUT  STD_LOGIC;    
	\oe5#\:    INOUT  STD_LOGIC;    
	\oe6#\:    IN     STD_LOGIC;    
	\oe7#\:    INOUT  STD_LOGIC;    
	OE_INV:    IN     STD_LOGIC;    
	PD:        IN     STD_LOGIC;    
	SCLK:      IN     STD_LOGIC;    
	SDATA:     INOUT  STD_LOGIC;    
	\src_div#\: INOUT  STD_LOGIC;    
	SRC_IN:    IN     STD_LOGIC;    
	\src_in#\: IN     STD_LOGIC;    
	SRC_STOP:  IN     STD_LOGIC;    
	VDD01:     IN     STD_LOGIC;    
	VDD02:     IN     STD_LOGIC;    
	VDD03:     IN     STD_LOGIC;    
	VDD04:     IN     STD_LOGIC;    
	VDD05:     IN     STD_LOGIC;    
	VDDA:      IN     STD_LOGIC);
end ics9db801;
