// generated by newgenasym  Wed Jun 07 14:31:05 2006


module ics9db801 (\bypass#/pll , dif_0, \dif_0# , dif_1, \dif_1# , dif_2, \dif_2# ,
        dif_3, \dif_3# , dif_4, \dif_4# , dif_5, \dif_5# , dif_6, \dif_6# ,
        dif_7, \dif_7# , gnd01, gnd02, gnd03, gnd04, gnd05, gnda,
        \high_bw# , iref, lock, \oe0# , \oe1# , \oe2# , \oe3# , \oe4# , \oe5# , \oe6# ,
        \oe7# , oe_inv, pd, sclk, sdata, \src_div# , src_in, \src_in# ,
        src_stop, vdd01, vdd02, vdd03, vdd04, vdd05, vdda);
    input \bypass#/pll ;
    inout dif_0;
    inout \dif_0# ;
    output dif_1;
    output \dif_1# ;
    output dif_2;
    output \dif_2# ;
    inout dif_3;
    inout \dif_3# ;
    inout dif_4;
    inout \dif_4# ;
    output dif_5;
    output \dif_5# ;
    output dif_6;
    output \dif_6# ;
    inout dif_7;
    inout \dif_7# ;
    inout gnd01;
    inout gnd02;
    inout gnd03;
    inout gnd04;
    inout gnd05;
    input gnda;
    input \high_bw# ;
    output iref;
    inout lock;
    inout \oe0# ;
    input \oe1# ;
    inout \oe2# ;
    inout \oe3# ;
    inout \oe4# ;
    inout \oe5# ;
    input \oe6# ;
    inout \oe7# ;
    input oe_inv;
    input pd;
    input sclk;
    inout sdata;
    inout \src_div# ;
    input src_in;
    input \src_in# ;
    input src_stop;
    input vdd01;
    input vdd02;
    input vdd03;
    input vdd04;
    input vdd05;
    input vdda;


    initial
        begin
        end

endmodule
