-- generated by newgenasym Wed May 24 15:25:45 2006

library ieee;
use     ieee.std_logic_1164.all;
use     work.all;
entity PCA9555 is
    port (    
	A0:        IN     STD_LOGIC;    
	A1:        IN     STD_LOGIC;    
	A2:        IN     STD_LOGIC;    
	\i/o0.0\:  INOUT  STD_LOGIC;    
	\i/o0.1\:  INOUT  STD_LOGIC;    
	\i/o0.2\:  INOUT  STD_LOGIC;    
	\i/o0.3\:  INOUT  STD_LOGIC;    
	\i/o0.4\:  INOUT  STD_LOGIC;    
	\i/o0.5\:  INOUT  STD_LOGIC;    
	\i/o0.6\:  INOUT  STD_LOGIC;    
	\i/o0.7\:  INOUT  STD_LOGIC;    
	\i/o1.0\:  INOUT  STD_LOGIC;    
	\i/o1.1\:  INOUT  STD_LOGIC;    
	\i/o1.2\:  INOUT  STD_LOGIC;    
	\i/o1.3\:  INOUT  STD_LOGIC;    
	\i/o1.4\:  INOUT  STD_LOGIC;    
	\i/o1.5\:  INOUT  STD_LOGIC;    
	\i/o1.6\:  INOUT  STD_LOGIC;    
	\i/o1.7\:  INOUT  STD_LOGIC;    
	\int#\:    OUT    STD_LOGIC;    
	SCL:       IN     STD_LOGIC;    
	SDA:       INOUT  STD_LOGIC;    
	VDD:       IN     STD_LOGIC;    
	VSS:       IN     STD_LOGIC);
end PCA9555;
