-- generated by newgenasym Thu Apr 27 11:44:15 2006

library ieee;
use     ieee.std_logic_1164.all;
use     work.all;
entity en5330 is
    port (    
	AGND:      INOUT  STD_LOGIC;    
	AVIN:      INOUT  STD_LOGIC;    
	COMP:      INOUT  STD_LOGIC;    
	EAIN:      INOUT  STD_LOGIC;    
	EAOUT:     INOUT  STD_LOGIC;    
	ENABLE:    INOUT  STD_LOGIC;    
	NC1:       INOUT  STD_LOGIC;    
	NC2:       INOUT  STD_LOGIC;    
	PGND1:     INOUT  STD_LOGIC;    
	PGND2:     INOUT  STD_LOGIC;    
	PGND3:     INOUT  STD_LOGIC;    
	PGND4:     INOUT  STD_LOGIC;    
	PGND5:     INOUT  STD_LOGIC;    
	PGND6:     INOUT  STD_LOGIC;    
	PGND7:     INOUT  STD_LOGIC;    
	PGND8:     INOUT  STD_LOGIC;    
	PGND_PAD:  INOUT  STD_LOGIC;    
	POK:       INOUT  STD_LOGIC;    
	PVIN1:     INOUT  STD_LOGIC;    
	PVIN2:     INOUT  STD_LOGIC;    
	PVIN3:     INOUT  STD_LOGIC;    
	PVIN4:     INOUT  STD_LOGIC;    
	ROCP:      INOUT  STD_LOGIC;    
	SOFTSTART: INOUT  STD_LOGIC;    
	VDRAIN:    INOUT  STD_LOGIC;    
	VOUT1:     INOUT  STD_LOGIC;    
	VOUT2:     INOUT  STD_LOGIC;    
	VOUT3:     INOUT  STD_LOGIC;    
	VOUT4:     INOUT  STD_LOGIC;    
	VOUT5:     INOUT  STD_LOGIC;    
	VOUT6:     INOUT  STD_LOGIC;    
	VOUT_PAD:  INOUT  STD_LOGIC;    
	VS0:       INOUT  STD_LOGIC;    
	VS1:       INOUT  STD_LOGIC;    
	VS2:       INOUT  STD_LOGIC;    
	VSENSE:    INOUT  STD_LOGIC;    
	XFB:       INOUT  STD_LOGIC;    
	XOV:       INOUT  STD_LOGIC);
end en5330;
