-- generated by newgenasym Thu Jun 01 15:09:54 2006

library ieee;
use     ieee.std_logic_1164.all;
use     work.all;
entity ics55703 is
    port (    
	CKL1N:     OUT    STD_LOGIC;    
	CLK0N:     OUT    STD_LOGIC;    
	CLK0P:     OUT    STD_LOGIC;    
	CLK1P:     OUT    STD_LOGIC;    
	GNDODA:    IN     STD_LOGIC;    
	GNDXD:     IN     STD_LOGIC;    
	IREF:      OUT    STD_LOGIC;    
	OE:        IN     STD_LOGIC;    
	S0:        IN     STD_LOGIC;    
	S1:        IN     STD_LOGIC;    
	SS0:       IN     STD_LOGIC;    
	SS1:       IN     STD_LOGIC;    
	VDDODA:    IN     STD_LOGIC;    
	VDDXD:     IN     STD_LOGIC;    
	\x1/iclk\: IN     STD_LOGIC;    
	X2:        OUT    STD_LOGIC);
end ics55703;
