-- generated by newgenasym Thu Jun 08 17:04:32 2006

library ieee;
use     ieee.std_logic_1164.all;
use     work.all;
entity hdr_1x4 is
    port (    
	A1:        INOUT  STD_LOGIC;    
	A2:        INOUT  STD_LOGIC;    
	A3:        INOUT  STD_LOGIC;    
	A4:        INOUT  STD_LOGIC);
end hdr_1x4;
