-- generated by newgenasym Fri Sep 08 10:08:47 2006

library ieee;
use     ieee.std_logic_1164.all;
use     work.all;
entity stiff_6p is
    port (    
	A0:        INOUT  STD_LOGIC;    
	A1:        INOUT  STD_LOGIC;    
	A2:        INOUT  STD_LOGIC;    
	A3:        INOUT  STD_LOGIC;    
	A4:        INOUT  STD_LOGIC;    
	A5:        INOUT  STD_LOGIC);
end stiff_6p;
