// generated by newgenasym  Thu Feb 01 17:09:04 2007


module \24lc512  (a0, a1, a2, gnd, scl, sda, vcc, wp);
    input a0;
    input a1;
    input a2;
    input gnd;
    input scl;
    inout sda;
    input vcc;
    input wp;


    initial
        begin
        end

endmodule
