-- generated by newgenasym Thu Feb 01 17:09:04 2007

library ieee;
use     ieee.std_logic_1164.all;
use     work.all;
entity \24lc512\ is
    port (    
	A0:        IN     STD_LOGIC;    
	A1:        IN     STD_LOGIC;    
	A2:        IN     STD_LOGIC;    
	GND:       IN     STD_LOGIC;    
	SCL:       IN     STD_LOGIC;    
	SDA:       INOUT  STD_LOGIC;    
	VCC:       IN     STD_LOGIC;    
	WP:        IN     STD_LOGIC);
end \24lc512\;
