-- *************************************************************** -- Company: Integrated Device Technology, Inc. -- -- Part : CM8A34001 -- -- Title: BSDL file of CM8A34001 -- Generated by : SZ -- -- Release status: formal issue -- Security level: client use -- BSDL Version 2001 -- Revision History: -- Mar 19, 2018: initial release -- Jun 01, 2018: fixed syntax error (AS) -- Jun 05, 2018: ID[4:0] == [vss,vss,nc,vss,nc] == variant5 == 0x635 -- -- Generated by boundaryScanGenerate 2015.2-p1 -- BSDL Version 2001 entity CM8A34001 is generic (PHYSICAL_PIN_MAP : string := "BGA_144"); port ( -- Port List OSCI : linkage bit; OSCO : linkage bit; CREG_XTAL : linkage bit; nMR : in bit; nTEST : in bit; FILTER : linkage bit; CAP_REF : linkage bit; SCL_M : inout bit; SDA_M : inout bit; SCLK : inout bit; SCLK_AUX : linkage bit; SDIO : inout bit; SDIO_AUX : linkage bit; SDI_A1 : inout bit; SDI_A1_AUX : linkage bit; CS_A0 : inout bit; CS_A0_AUX : linkage bit; XO_DPLL : linkage bit; TP1 : linkage bit; TP2 : linkage bit; CLK0 : linkage bit; CLK1 : linkage bit; CLK2 : linkage bit; CLK3 : linkage bit; CLK4 : linkage bit; CLK5 : linkage bit; CLK6 : linkage bit; CLK7 : linkage bit; nCLK0 : linkage bit; nCLK1 : linkage bit; nCLK2 : linkage bit; nCLK3 : linkage bit; nCLK4 : linkage bit; nCLK5 : linkage bit; nCLK6 : linkage bit; nCLK7 : linkage bit; Q0 : linkage bit; Q1 : linkage bit; Q2 : linkage bit; Q3 : linkage bit; Q4 : linkage bit; Q5 : linkage bit; Q6 : linkage bit; Q7 : linkage bit; Q8 : linkage bit; Q9 : linkage bit; Q10 : linkage bit; Q11 : linkage bit; nQ0 : linkage bit; nQ1 : linkage bit; nQ2 : linkage bit; nQ3 : linkage bit; nQ4 : linkage bit; nQ5 : linkage bit; nQ6 : linkage bit; nQ7 : linkage bit; nQ8 : linkage bit; nQ9 : linkage bit; nQ10 : linkage bit; nQ11 : linkage bit; GPIO_DC0 : in bit; GPIO_DC1 : in bit; GPIO_DC2 : in bit; GPIO_DC3 : out bit; GPIO_DC4 : in bit; GPIO_DC5 : inout bit; GPIO_DC6 : inout bit; GPIO_DC7 : inout bit; GPIO_DC8 : inout bit; GPIO_DC9 : inout bit; GPIO_DC10 : inout bit; GPIO_DC11 : inout bit; GPIO_DC12 : inout bit; GPIO_DC13 : inout bit; GPIO_DC14 : inout bit; GPIO_DC15 : inout bit; VDDA_XTAL : linkage bit; VDDA_FB : linkage bit; VDDA_LC : linkage bit; VDDA_PDCP : linkage bit; VDDA_BG : linkage bit; VDD_DCO_Q0Q1 : linkage bit; VDD_DCO_Q2Q3 : linkage bit; VDD_DCO_Q4Q5 : linkage bit; VDD_DCO_Q6Q7 : linkage bit; VDD_DCO_Q8 : linkage bit; VDD_DCO_Q9 : linkage bit; VDD_DCO_Q10 : linkage bit; VDD_DCO_Q11 : linkage bit; VDD_GPIO : linkage bit; VDD_DIG : linkage bit_vector(1 downto 0); VDD_DIA_A : linkage bit; VDD_DIA_B : linkage bit; VDD_CLKA : linkage bit; VDD_CLKB : linkage bit; VDDO_Q0 : linkage bit; VDDO_Q1 : linkage bit; VDDO_Q2 : linkage bit; VDDO_Q3 : linkage bit; VDDO_Q4 : linkage bit; VDDO_Q5 : linkage bit; VDDO_Q6 : linkage bit; VDDO_Q7 : linkage bit; VDDO_Q8 : linkage bit; VDDO_Q9 : linkage bit; VDDO_Q10 : linkage bit; VDDO_Q11 : linkage bit; VSSD : linkage bit_vector(1 downto 0); VSS : linkage bit_vector(32 downto 0)); use STD_1149_1_2001.all; use LVS_BSCAN_CELLS.all; attribute COMPONENT_CONFORMANCE of CM8A34001: entity is "STD_1149_1_2001"; --Pin mappings attribute PIN_MAP of CM8A34001: entity is PHYSICAL_PIN_MAP; constant BGA_144: PIN_MAP_STRING := "OSCI : B4 , " & "OSCO : A4 , " & "CREG_XTAL : C4 , " & "nMR : L10 , " & "nTEST : M10 , " & "FILTER : M4 , " & "CAP_REF : L4 , " & "SCL_M : B3 , " & "SDA_M : A2 , " & "SCLK : K2 , " & "SCLK_AUX : M1 , " & "SDIO : L2 , " & "SDIO_AUX : L1 , " & "SDI_A1 : M2 , " & "SDI_A1_AUX : K1 , " & "CS_A0 : M3 , " & "CS_A0_AUX : L3 , " & "XO_DPLL : A1 , " & "TP1 : M7 , " & "TP2 : L7 , " & "CLK0 : B1 , " & "CLK1 : C1 , " & "CLK2 : D1 , " & "CLK3 : E1 , " & "CLK4 : F1 , " & "CLK5 : G1 , " & "CLK6 : H1 , " & "CLK7 : J1 , " & "nCLK0 : B2 , " & "nCLK1 : C2 , " & "nCLK2 : D2 , " & "nCLK3 : E2 , " & "nCLK4 : F2 , " & "nCLK5 : G2 , " & "nCLK6 : H2 , " & "nCLK7 : J2 , " & "Q0 : A8 , " & "Q1 : A9 , " & "Q2 : A11 , " & "Q3 : A12 , " & "Q4 : M12 , " & "Q5 : M11 , " & "Q6 : M9 , " & "Q7 : M8 , " & "Q8 : A6 , " & "Q9 : E12 , " & "Q10 : H12 , " & "Q11 : M6 , " & "nQ0 : B8 , " & "nQ1 : B9 , " & "nQ2 : B11 , " & "nQ3 : B12 , " & "nQ4 : L12 , " & "nQ5 : L11 , " & "nQ6 : L9 , " & "nQ7 : L8 , " & "nQ8 : B6 , " & "nQ9 : E11 , " & "nQ10 : H11 , " & "nQ11 : L6 , " & "GPIO_DC0 : A10 , " & "GPIO_DC1 : F11 , " & "GPIO_DC2 : F12 , " & "GPIO_DC3 : J11 , " & "GPIO_DC4 : B10 , " & "GPIO_DC5 : D11 , " & "GPIO_DC6 : D12 , " & "GPIO_DC7 : G11 , " & "GPIO_DC8 : G12 , " & "GPIO_DC9 : J12 , " & "GPIO_DC10 : M5 , " & "GPIO_DC11 : A3 , " & "GPIO_DC12 : B5 , " & "GPIO_DC13 : A5 , " & "GPIO_DC14 : B7 , " & "GPIO_DC15 : A7 , " & "VDDA_XTAL : D4 , " & "VDDA_FB : E5 , " & "VDDA_LC : K4 , " & "VDDA_PDCP : E4 , " & "VDDA_BG : J5 , " & "VDD_DCO_Q0Q1 : D9 , " & "VDD_DCO_Q2Q3 : D8 , " & "VDD_DCO_Q4Q5 : J8 , " & "VDD_DCO_Q6Q7 : J9 , " & "VDD_DCO_Q8 : D7 , " & "VDD_DCO_Q9 : F9 , " & "VDD_DCO_Q10 : G9 , " & "VDD_DCO_Q11 : J7 , " & "VDD_GPIO : J4 , " & "VDD_DIG : (G5, H57), " & "VDD_DIA_A : F7 , " & "VDD_DIA_B : G7 , " & "VDD_CLKA : G3 , " & "VDD_CLKB : H3 , " & "VDDO_Q0 : C8 , " & "VDDO_Q1 : C9 , " & "VDDO_Q2 : C11 , " & "VDDO_Q3 : C12 , " & "VDDO_Q4 : K12 , " & "VDDO_Q5 : K11 , " & "VDDO_Q6 : K9 , " & "VDDO_Q7 : K8 , " & "VDDO_Q8 : C6 , " & "VDDO_Q9 : E10 , " & "VDDO_Q10 : H10 , " & "VDDO_Q11 : K6 , " & "VSSD : (G4 , H4), " & "VSS : (C3, C5, C7, C10, D3, D5, D6, D10, E3, E6, " & "E7, E8, E9, F3, F4, F5, F6, F8, F10, G6, " & "G8, G10, H6, H7, H8, H9, J3, J6, J10, K3, " & "K7, K10, L5) " ; attribute TAP_SCAN_RESET of GPIO_DC4 : signal is true; attribute TAP_SCAN_IN of GPIO_DC2 : signal is true; attribute TAP_SCAN_MODE of GPIO_DC1 : signal is true; attribute TAP_SCAN_OUT of GPIO_DC3 : signal is true; attribute TAP_SCAN_CLOCK of GPIO_DC0 : signal is (1.0000000000000000000e+07, BOTH); attribute COMPLIANCE_PATTERNS of CM8A34001 : entity is "(nTEST) (0)"; attribute INSTRUCTION_LENGTH of CM8A34001: entity is 18; attribute INSTRUCTION_OPCODE of CM8A34001: entity is "IDCODE (111111111111111110)," & "BYPASS (111111111111111111)," & "EXTEST (111111111111101000)," & "SAMPLE (111111111111111000)," & "PRELOAD (111111111111111000)," & "HIGHZ (111111111111001111)," & "CLAMP (111111111111101111) " ; attribute INSTRUCTION_CAPTURE of CM8A34001: entity is "xxxxxxxxxxxxxxxx01"; attribute IDCODE_REGISTER of CM8A34001: entity is "0000" & -- version "0000011000110101" & -- part number "00000110011" & -- manufacturer's identity "1"; -- required by 1149.1 attribute REGISTER_ACCESS of CM8A34001: entity is "DEVICE_ID ( IDCODE ), " & "BOUNDARY ( SAMPLE, PRELOAD, EXTEST )," & "BYPASS ( HIGHZ, CLAMP, BYPASS ) " ; --Boundary scan definition attribute BOUNDARY_LENGTH of CM8A34001: entity is 43; attribute BOUNDARY_REGISTER of CM8A34001: entity is -- num cell port function safe [ccell disval rslt] " 42 (BC_4 , nMR , observe_only , X ) ,"& " 41 (BC_2 , * , control , 1 ) ,"& " 40 (LV_BC_7 , SCL_M , bidir , X , 41 , 1 , Z ),"& " 39 (BC_2 , * , control , 1 ) ,"& " 38 (LV_BC_7 , SDA_M , bidir , X , 39 , 1 , Z ),"& " 37 (BC_2 , * , control , 1 ) ,"& " 36 (LV_BC_7 , SCLK , bidir , X , 37 , 1 , Z ),"& " 35 (BC_2 , * , control , 1 ) ,"& " 34 (LV_BC_7 , SDIO , bidir , X , 35 , 1 , Z ),"& " 33 (BC_2 , * , control , 1 ) ,"& " 32 (LV_BC_7 , SDI_A1 , bidir , X , 33 , 1 , Z ),"& " 31 (BC_2 , * , control , 1 ) ,"& " 30 (LV_BC_7 , CS_A0 , bidir , X , 31 , 1 , Z ),"& " 29 (BC_0 , * , internal , 0 ) ,"& " 28 (BC_0 , * , internal , 0 ),"& " 27 (BC_0 , * , internal , 0 ) ,"& " 26 (BC_0 , * , internal , 0 ),"& " 25 (BC_0 , * , internal , 0 ) ,"& " 24 (BC_0 , * , internal , 0 ),"& " 23 (BC_0 , * , internal , 0 ) ,"& " 22 (BC_0 , * , internal , 0 ),"& " 21 (BC_2 , * , control , 1 ) ,"& " 20 (LV_BC_7 , GPIO_DC5 , bidir , X , 21 , 1 , Z ),"& " 19 (BC_2 , * , control , 1 ) ,"& " 18 (LV_BC_7 , GPIO_DC6 , bidir , X , 19 , 1 , Z ),"& " 17 (BC_2 , * , control , 1 ) ,"& " 16 (LV_BC_7 , GPIO_DC7 , bidir , X , 17 , 1 , Z ),"& " 15 (BC_2 , * , control , 1 ) ,"& " 14 (LV_BC_7 , GPIO_DC8 , bidir , X , 15 , 1 , Z ),"& " 13 (BC_2 , * , control , 1 ) ,"& " 12 (LV_BC_7 , GPIO_DC9 , bidir , X , 13 , 1 , Z ),"& " 11 (BC_2 , * , control , 1 ) ,"& " 10 (LV_BC_7 , GPIO_DC10 , bidir , X , 11 , 1 , Z ),"& " 9 (BC_2 , * , control , 1 ) ,"& " 8 (LV_BC_7 , GPIO_DC11 , bidir , X , 9 , 1 , Z ),"& " 7 (BC_2 , * , control , 1 ) ,"& " 6 (LV_BC_7 , GPIO_DC12 , bidir , X , 7 , 1 , Z ),"& " 5 (BC_2 , * , control , 1 ) ,"& " 4 (LV_BC_7 , GPIO_DC13 , bidir , X , 5 , 1 , Z ),"& " 3 (BC_2 , * , control , 1 ) ,"& " 2 (LV_BC_7 , GPIO_DC14 , bidir , X , 3 , 1 , Z ),"& " 1 (BC_2 , * , control , 1 ) ,"& " 0 (LV_BC_7 , GPIO_DC15 , bidir , X , 1 , 1 , Z ) "; end CM8A34001; -- VHDL package to be uploaded --package LVS_BSCAN_CELLS is -- use STD_1149_1_2001.all; -- constant LV_BC_7: CELL_INFO; -- --end LVS_BSCAN_CELLS; --package body LVS_BSCAN_CELLS is -- use STD_1149_1_2001.all; -- constant LV_BC_7: CELL_INFO := -- ((BIDIR_IN, EXTEST, PI), (BIDIR_OUT, EXTEST, PO), -- (BIDIR_IN, SAMPLE, PI), (BIDIR_OUT, SAMPLE, PI), -- (BIDIR_IN, INTEST, X), (BIDIR_OUT, INTEST, PI)); -- --end LVS_BSCAN_CELLS; --