Zynq UltraScale+ MPSoC reference design set up for always-on and optimized for PL performance.

Features

  • Gives highest device performance but consumes more power
  • SW control of advanced Processing System (PS) power management schemes only; No access to low power (~mW) states
  • Simple power supply requirements – large number of rails grouped; Generally applicable to the -3E speed grade devices
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Always On: PL Performance-Optimized Rail Consolidation
Always On: PL Performance-Optimized Rail Consolidation
Rail Voltage Power Supply Rails
Rail 1 0.85/0.9V VCCINT, VCC_PSINTFP, VCC_PSINTLP, VCC_PSINTFP_DDR, VCCINT_VCU, VCCINT_IO, VCCBRAM
Rail 2* 1.8V* VCC_PSAUX, VCCAUX, VCCAUX_IO, VCC_PSDDR_PLL, VCCADC, VCC_PSADC
Rail 3* 1.2V* VMGTAVTT (GTH), VMGTYAVTT (GTY), VCC_PSPLL
Rail 4 1.1-1.5V VCCO_PSDDR
Rail 5 1.8-3.3V VCCO_PSIO
Rail 6* 1.8V* VMGTVCCAUX (GTH), VMGTYVCCAUX (GTY), VPS_MGTRAVTT
Rail 7* 0.9V* VMGTAVCC (GTH), VMGTYAVCC (GTY), VPS_MGTRAVCC
Rail 8 1.2-3.3V HDIO_VCCO
Rail 9 1-1.8V HPIO_VCCO

* Please see the Xilinx UltraScale Architecture PCB Design User Guide for additional rail specifications.

 


Use Case 3.1 for ZU2 – ZU3

High Load Rails

  • Rail 1 = 6.15-7.57A

Reference Design Files

Recommended Parts

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Zynq UltraScale+ MPSoC Use Case 3.1

Use Case 3.2 for ZU4 – ZU5

High Load Rails

  • Rail 1 = 9.95-15.25A

Reference Design Files

Recommended Parts

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Zynq UltraScale+ MPSoC Use Case 3.2

Use Case 3.3 for ZU6 – ZU9

High Load Rails

  • Rail 1 = 18.25-23.95A
  • Rail 3 = 2.1A
  • Rail 7 = 2.3A

Reference Design Files

Recommended Parts

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Zynq UltraScale+ MPSoC Use Case 3.3

Use Case 3.4 for ZU11 – ZU19

High Load Rails

  • Rail 1 = 26.15-35.35A
  • Rail 2 = 1.54-2.04A
  • Rail 3 = 2.6-10.6A
  • Rail 7 = 2.8-7.8A

Reference Design Files

Recommended Parts

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Zynq UltraScale+ MPSoC Use Case 3.4

memoryBoards & Kits

Part Number Title Type Company
ISLUSPLUS-UC1DEMO1Z Power Supply Reference Demo Board for the Xilinx Zynq Ultrascale+™ MPSoC Demonstration Renesas
ISLUSPLUS-UC2DEMO1Z Power Supply Reference Demo Board for the Xilinx Zynq Ultrascale+™ MPSoC Demonstration Renesas