The SH7751R is a 32-bit RISC (reduced instruction set computer) microprocessor, featuring a built-in PCI bus controller compatible with PCs and multimedia devices.
It includes the SH-4 CPU, which at the object code level is upwardly compatible with the SH-1, SH-2, and SH-3 microcomputers. The SH7751R has an instruction cache, an operand cache that can be switched between copy-back and write-through modes, a 4-entry full associative instruction TLB (table look aside buffer), and MMU (memory management unit) with 64-entry full-associative shared TLB.
The SH7751R also includes a bus state controller (BSC) that can be coupled to synchronous DRAM. Also, because of its built in functions, such as PCI bus controller, timers, and serial communications functions, required for multimedia and OA equipment, use of the SH7751R enables a dramatic reduction in system costs.
- Operating frequency
- Large capaciy Cache: 16kB instruction + 32kB data
- (2way set associative)
- H-UDI, UBC, AUD
- BGA256, QFP256
- Other features
- PCI bus controller
- Pin compatible with the SH7751
Pin Count / Memory Size Lineup：
Below you will find information to support the development of your application.
You can find an explanation of orderable part numbers here.
Resources for Software and Hardware
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Hardware Design Support
|IBIS/BSDL||IBIS standard simulation data is required for high-speed board design and can be used to run simulations to examine and troubleshoot issues such as waveform reflection, ringing, and so on, before producing the actual board.
BSDL is a data input format supported by most IEEE 1149.1 (JTAG)-compliant tools. The automatic test pattern generation (ATPG) and automatic test equipment functions of these tools facilitate testing.
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