The SH7450 and SH7451 Groups are high-performance RISC microcontrollers embedded with a 32-bit SH-4A CPU core.
They have a maximum operating frequency of 240 MHz, CPU performance of over 432 MIPS, support single and double-precision floating point arithmetic operations, and achieve a maximum single-precision performance of 1.68 GFLOPS.
They incorporate enhanced communication functions required for in-vehicle networks, such as 5 channels of CAN and 2 channels of FlexRay (SH7450). The SH7450 and SH7451 also incorporate camera interface functions required for in-vehicle camera control such as DRI interface (3 channels) and I2C-bus interface (1 channel), and components required for in-vehicle millimeter wave systems such as PDAC, PSEL, and DRI circuits, Timer unit TMU(3 channels), and multifunction timer unit ATU-IIIS (62 channels). Furthermore, an on-chip inter-board communication function for multi-CPU configurations enables higher performance driver-assist systems.
- Operating frequency: 240 MHz
- CPU: 432 MIPS, FPU: 1.68 GFLOPS
- On-chip large capacity memory
- ROM: 2 MB (SH7450), 1.5 MB (SH7451)
- RAM: 512 KB + 8 KB + 16 KB (Total: 536 KB)
high-speed RAM for instruction: 8 KB, high-speed RAM for data: 16 KB, medium-speed large capacity RAM: 512 KB
- Cache memory: divided into 32 Kbytes instruction and 32 Kbytes data, 4-way set associative
- FlexRay*module (compliant with FlexRay 2.1 specifications): 1module (2ch)
- Peripheral functions
- Timer ATU-IIIS: 62 ch
- A/D converter: 12-bit, 24 ch (16 + 8) 2 modules
- Direct memory access controller (DMAC): 12 ch
- Direct RAM input interface (DRI): 3 ch
- Direct RAM output interface (DRO): 1 ch
- Parallel DAC control interface (PDAC): 1 ch
- Parallel selector (PSEL): 1 ch
- Serial communication interface: 8 ch
- Controller area network (CAN): 5 ch (64 message slot）
- Clock generator: multiplication PLL
- On-chip debugging function (H-UDI)
- RAM monitor function (AUDR)
- Package: BGA292 (17 mm x 17 mm, 0.8 mm pin pitch）
*FlexRay is a registered trademark of Daimler Chrysler AG. Only the SH7450 has 1module (2 ch).
Pin Count / Memory Size Lineup:
Below you will find information to support the development of your application.
You can find an explanation of orderable part numbers here.
Resources for Software and Hardware
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Hardware Design Support
IBIS standard simulation data is required for high-speed board design and can be used to run simulations to examine and troubleshoot issues such as waveform reflection, ringing, and so on, before producing the actual board.
BSDL is a data input format supported by most IEEE 1149.1 (JTAG)-compliant tools. The automatic test pattern generation (ATPG) and automatic test equipment functions of these tools facilitate testing.
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