High-Speed Embedded AI-Based Image Processing Device with Dynamically Reconfigurable Processor (DRP) Technology
The RZ/A2M MPU is designed for e-AI based imaging in smart appliances, networked cameras, service robots, scanner products, and industrial machinery that require high-speed image processing. It features a unique hybrid approach to image recognition and machine vision by combining proprietary DRP technology for fast pre-processing of image data and feature extraction, closely coupled to an Arm® Cortex®-A9 CPU for AI inferencing.
RZ/A2M Wins Electronics Products’ 2018 Product of the Year Award
The RZ/A2M microprocessor (MPU) with Dynamically Reconfigurable Processor (DRP) technology was selected as a winner of Electronic Products’ prestigious Product of the Year Award in the MPUs and MCUs category. The DRP is based on a massively parallel wired logic architecture that can execute different operations on different data sets at each processor cycle. This allows the RZ/A2M to deliver real-time image processing at low power consumption with complete flexibility, and at 10x the performance of its predecessor, the RZ/A1. RZ/A2M innovation also includes 4 MB of on-chip SRAM, MIPI camera interface, a two-channel Ethernet interface, and hardware security features for crypto acceleration and establishing a Root of Trust.
Main Solutions
Key Features:
| Item | RZ/A2M | |
|---|---|---|
| Part name/use/package | 176 pin | R7S921040VCBG |
| Industry usage etc. | ||
| 176-pinBGA (13mm×13mm) 0.8mm pitch |
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| 256 pin | R7S921041VCBG | |
| Industry usage etc. | ||
| 256-pinBGA (11mm×11mm) 0.5mm pitch |
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| R7S921051VCBG | ||
| Industry usage etc. | ||
| 256-pinBGA (11mm×11mm) 0.5mm pitch |
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| 272 pin | R7S921042VCBG | |
| Industry usage etc. | ||
| 272-pinBGA (17mm×17mm) 0.8mm pitch |
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| R7S921052VCBG | ||
| Industry usage etc. | ||
| 272-pinBGA (17mm×17mm) 0.8mm pitch |
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| 324 pin | R7S921043VCBG | |
| Industry usage etc. | ||
| 324-pinBGA (19mm×19mm) 0.8mm pitch |
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| R7S921053VCBG | ||
| Industry usage etc. | ||
| 324-pinBGA (19mm×19mm) 0.8mm pitch |
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| Power supply voltage | 3.3V/1.8V/1.2V | |
| Maximum operating frequency | 528MHz | |
| CPU core | Arm® Cortex®-A9(with Jazelle® and NEON™) | |
| On-chip RAM | Large-capacity memory: 4MB | |
| (For video display/work area; 128 KB are shared with data retention) | ||
| Cache memory | Primary cache memory: 64 KB (separated 32K instruction/32K data, TLB128 entry) Secondary cache memory: 128 KB (with CoreLink™ Level 2 Cache Controller L2C-310) |
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| External memory | Bus clock: up to 132 MHz | |
| Direct connection to SRAM, byte select SRAM, SDRAM, and burst ROM (clock synchronous/clock asynchronous) using bus state controller. Address/data multiplexer I/O (MPX) interface supported. |
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| Address space: 64 MB x 6 | ||
| Data bus width: external 8/16 bits | ||
| Graphics functions | Video display controller(1 channel of video input and 1 channel of panel output which supports LVDS) | |
| Sprite engine | ||
| Capture engine unit (CMOS camera interface) | ||
| Distortion correction engine x 1 channel (requires nondisclosure agreement) | ||
| 2D drawing Engine | ||
| MIPI CSI-2 interface | ||
| JPEG codec unit | ||
| Audio functions | Serial sound interface x 4 channels | |
| Renesas SPDIF interface | ||
| Timer functions | Multifunction 16-bit timer (MTU3) x 8 channels, 32-bit timer x 1 channel | |
| 32-bit OS timer x 3 channels | ||
| Motor control PWM timer x 8 channels | ||
| Watchdog timer | ||
| Real-time clock | ||
| Connectivity functions | USB 2.0 host/function module x 2 channels (host or function selectable) | |
| SD/MMC host interface x 2 channels (must obtain SD card license) | ||
| NAND flash interface | ||
| Ethernet controller (10 Mbps/100 Mbps transfer, IEEE802.3 PHY interface MII and RMII) | ||
| SPI multi I/O bus controller x 1 channel (Up to two serial flash memories with multiple I/O bus sizes (single/quad) can be connected to 1 channel/ Connectable with one HyperFlash™ memory, direct execution from CPU supported) | ||
| HyperBus™ controller | ||
| Octa memory controller | ||
| Serial communication interface with 16-stage FIFO (SCIF) x 5 channels (asynchronous and clock synchronous serial communication possible) | ||
| Serial communication interface x 2 channels (smart card interface, IrDA 1.0) | ||
| Renesas serial peripheral interface x 3 channels | ||
| I2C bus interface x 4 channels | ||
| Controller area network (CAN) x 2 channels (CAN-FD supported) | ||
| System analog functions | Clock pulse generator (CPG): built-in PLL, maximum 32 times multiplication, built-in SSCG circuit | |
| Direct memory access controller x 16 channels | ||
| Interrupt controller (with Arm® PrimeCell® Generic Interrupt Controller [GIC-400]) | ||
| A/D converter (12-bit resolution) x 8 channels | ||
| Debugging interface CoreSight™ architecture JTAG standard pin layout |
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| Optional function | Dynamically Reconfigurable Processor (DRP) | |
| Secure features (requires nondisclosure agreement) | ||
| Boot modes | Boot mode 0: Booting from memory (bus width: 16 bits) connected to the CS0 space | |
| Boot mode 1: Booting from a NAND flash memory with SD controller | ||
| Boot mode 2: Booting from a NAND flash memory with MMC controller | ||
| Boot mode 3: Booting from a serial NOR flash memory (3.3 V) connected to the SPI multi I/O bus space | ||
| Boot mode 4: Booting from a OctaFlash™ connected to the SPI multi I/O bus space | ||
| Boot mode 5: Booting from a HyperFlash™ connected to the SPI multi I/O bus space | ||
| Boot mode 6: Booting from a OctaFlash™ connected to the OctaFlash™ space | ||
| Boot mode 7: Booting from a HyperFlash™ connected to the HyperFlash™ space | ||
| Power-down modes | Sleep mode | |
| Software standby mode | ||
| Deep standby mode | ||
| Module standby mode | ||
Block Diagram:
*Arm, Cortex, CoreLink, and CoreSight are registered trademarks or trademarks of Arm Limited.
CAN (Controller Area Network): An automotive network specification developed by Robert Bosch GmbH of Germany.
All other names of products or services mentioned here are trademarks or registered trademarks of their respective owners.
Related Videos
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Renesas RZ/A2M microprocessors offer an innovative architecture based on the ARM Cortex®-A9 processor and industry-leading 4MB of on-chip memory.
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Resources for Software and Hardware
| Title | Description |
|---|---|
| e2 studio | Renesas eclipse embedded studio, known as e² studio, is a complete development and debug environment based on the popular Eclipse CDT project. |
Resources for Software
| Title | Description |
|---|---|
| Register definition | To be able to use as specified variables, this iodefine.h is defined the peripheral I/O registers. |
Hardware Design Support
| Title | Description |
|---|---|
| IBIS/BSDL | IBIS standard simulation data is required for high-speed board design and can be used to run simulations to examine and troubleshoot issues such as waveform reflection, ringing, and so on, before producing the actual board. BSDL is a data input format supported by most IEEE 1149.1 (JTAG)-compliant tools. The automatic test pattern generation (ATPG) and automatic test equipment functions of these tools facilitate testing. |
| Oscillation circuit characteristics | Please search for your resonator on its manufacturer's site linked below. If you require optimal oscillation circuit constants for your particular system, please ask the manufacturer of the oscillator. For main clock resonators: KYOCERA: Click for oscillation evaluation result. |
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