10 times the image processing ability of the conventional! Secure and safe network connection realized with enhanced security function. Key device of image recognition application
RZ/A2M is suitable for applications using HMI (Human Machine Interface), among others, cameras. It corresponds to the MIPI camera interface which is widely used in mobile devices and incorporates DRP (Dynamically Reconfigurable Processor) which processes the input image at high speed. In addition to installing two Ethernet channels, security is enhanced by a cryptographic hardware accelerator. The network connection becomes safe and secure, and it can be applied to image recognition application of a wide range of systems from home electronics to industrial equipment.
Main Solutions
Key Features:
| Item | RZ/A2M | |
|---|---|---|
| Part name/use/package | 176 pin | R7S921040VCBG |
| Industry usage etc. | ||
| 176-pinBGA (13mm×13mm) 0.8mm pitch |
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| 256 pin | R7S921041VCBG | |
| Industry usage etc. | ||
| 256-pinBGA (11mm×11mm) 0.5mm pitch |
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| R7S921051VCBG | ||
| Industry usage etc. | ||
| 256-pinBGA (11mm×11mm) 0.5mm pitch |
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| 272 pin | R7S921042VCBG | |
| Industry usage etc. | ||
| 272-pinBGA (17mm×17mm) 0.8mm pitch |
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| R7S921052VCBG | ||
| Industry usage etc. | ||
| 272-pinBGA (17mm×17mm) 0.8mm pitch |
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| 324 pin | R7S921043VCBG | |
| Industry usage etc. | ||
| 324-pinBGA (19mm×19mm) 0.8mm pitch |
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| R7S921053VCBG | ||
| Industry usage etc. | ||
| 324-pinBGA (19mm×19mm) 0.8mm pitch |
||
| Power supply voltage | 3.3V/1.8V/1.2V | |
| Maximum operating frequency | 528MHz | |
| CPU core | Arm® Cortex®-A9(with Jazelle® and NEON™) | |
| On-chip RAM | Large-capacity memory: 4MB | |
| (For video display/work area; 128 KB are shared with data retention) | ||
| Cache memory | Primary cache memory: 64 KB (separated 32K instruction/32K data, TLB128 entry) Secondary cache memory: 128 KB (with CoreLink™ Level 2 Cache Controller L2C-310) |
|
| External memory | Bus clock: up to 132 MHz | |
| Direct connection to SRAM, byte select SRAM, SDRAM, and burst ROM (clock synchronous/clock asynchronous) using bus state controller. Address/data multiplexer I/O (MPX) interface supported. |
||
| Address space: 64 MB x 6 | ||
| Data bus width: external 8/16 bits | ||
| Graphics functions | Video display controller(1 channel of video input and 1 channel of panel output which supports LVDS) | |
| Sprite engine | ||
| Capture engine unit (CMOS camera interface) | ||
| Distortion correction engine x 1 channel (requires nondisclosure agreement) | ||
| 2D drawing Engine | ||
| MIPI CSI-2 interface | ||
| JPEG codec unit | ||
| Audio functions | Serial sound interface x 4 channels | |
| Renesas SPDIF interface | ||
| Timer functions | Multifunction 16-bit timer (MTU3) x 8 channels, 32-bit timer x 1 channel | |
| 32-bit OS timer x 3 channels | ||
| Motor control PWM timer x 8 channels | ||
| Watchdog timer | ||
| Real-time clock | ||
| Connectivity functions | USB 2.0 host/function module x 2 channels (host or function selectable) | |
| SD/MMC host interface x 2 channels (must obtain SD card license) | ||
| NAND flash interface | ||
| Ethernet controller (10 Mbps/100 Mbps transfer, IEEE802.3 PHY interface MII and RMII) | ||
| SPI multi I/O bus controller x 1 channel (Up to two serial flash memories with multiple I/O bus sizes (single/quad) can be connected to 1 channel/ Connectable with one HyperFlash™ memory, direct execution from CPU supported) | ||
| HyperBus™ controller | ||
| Octa memory controller | ||
| Serial communication interface with 16-stage FIFO (SCIF) x 5 channels (asynchronous and clock synchronous serial communication possible) | ||
| Serial communication interface x 2 channels (smart card interface, IrDA 1.0) | ||
| Renesas serial peripheral interface x 3 channels | ||
| I2C bus interface x 4 channels | ||
| Controller area network (CAN) x 2 channels (CAN-FD supported) | ||
| System analog functions | Clock pulse generator (CPG): built-in PLL, maximum 32 times multiplication, built-in SSCG circuit | |
| Direct memory access controller x 16 channels | ||
| Interrupt controller (with Arm® PrimeCell® Generic Interrupt Controller [GIC-400]) | ||
| A/D converter (12-bit resolution) x 8 channels | ||
| Debugging interface CoreSight™ architecture JTAG standard pin layout |
||
| Optional function | Dynamically Reconfigurable Processor (DRP) | |
| Secure features (requires nondisclosure agreement) | ||
| Boot modes | Boot mode 0: Booting from memory (bus width: 16 bits) connected to the CS0 space | |
| Boot mode 1: Booting from a NAND flash memory with SD controller | ||
| Boot mode 2: Booting from a NAND flash memory with MMC controller | ||
| Boot mode 3: Booting from a serial NOR flash memory (3.3 V) connected to the SPI multi I/O bus space | ||
| Boot mode 4: Booting from a OctaFlash™ connected to the SPI multi I/O bus space | ||
| Boot mode 5: Booting from a HyperFlash™ connected to the SPI multi I/O bus space | ||
| Boot mode 6: Booting from a OctaFlash™ connected to the OctaFlash™ space | ||
| Boot mode 7: Booting from a HyperFlash™ connected to the HyperFlash™ space | ||
| Power-down modes | Sleep mode | |
| Software standby mode | ||
| Deep standby mode | ||
| Module standby mode | ||
Block Diagram:
*Arm, Cortex, CoreLink, and CoreSight are registered trademarks or trademarks of Arm Limited.
CAN (Controller Area Network): An automotive network specification developed by Robert Bosch GmbH of Germany.
All other names of products or services mentioned here are trademarks or registered trademarks of their respective owners.
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| Title | Description |
|---|---|
| My Renesas | Create a My Renesas account to use our tool download services, receive e-newsletter/update notifications, and take advantage of our other services. |
| e-learning | Information for studying and learning about microcontrollers and microprocessors. |
| FAQ | Frequently asked questions and useful hints for development. |
| Forum | A forum and community site to share technical information, questions and opinions with others who use Renesas products. |
Resources for Software and Hardware
| Title | Description |
|---|---|
| e2 studio | Renesas eclipse embedded studio, known as e² studio, is a complete development and debug environment based on the popular Eclipse CDT project. |
Resources for Software
| Title | Description |
|---|---|
| Register definition | To be able to use as specified variables, this iodefine.h is defined the peripheral I/O registers. |
Hardware Design Support
| Title | Description |
|---|---|
| IBIS/BSDL | IBIS standard simulation data is required for high-speed board design and can be used to run simulations to examine and troubleshoot issues such as waveform reflection, ringing, and so on, before producing the actual board. BSDL is a data input format supported by most IEEE 1149.1 (JTAG)-compliant tools. The automatic test pattern generation (ATPG) and automatic test equipment functions of these tools facilitate testing. |
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