概览

描述

The RC32504A is a small, low-power timing component designed to be placed immediately adjacent to a PHY, switch, ASIC or FPGA that requires several reference clocks with jitter performance less than 100fs. The RC32504A can act as a frequency synthesizer to locally generate the reference clock, a jitter attenuator to perform local clean-up and/or frequency translation of a centrally-supplied reference, a synchronous Ethernet equipment clock to perform passband filtering and clean-up of network-supplied references or as a DCO for frequency margining or OTN clock applications. 

特性

  • Jitter below 100fs RMS (10kHz to 20MHz)
  • Compliant with ITU-T G.8262 for synchronous Ethernet/OTN (EEC/OEC) and ITU-T G.8262.1 for enhanced synchronous Ethernet/OTN (eEEC/eOEC)
  • PLL core consists of fractional-feedback Analog PLL (APLL) which can optionally be steered by a Digital PLL (DPLL)
    • Operates from a 25MHz to 80MHz crystal or XO
    • APLL frequency independent of input/crystal frequency
    • Operates as a frequency synthesizer, jitter attenuator, synchronous equipment slave clock or Digitally Controlled Oscillator (DCO)
    • DPLL loop filter programmable from 0.1Hz to 12kHz
    • DCO has tuning granularity of < 1ppb
  • Programmable input buffer supports HCSL, LVDS, or two LVCMOS with no external terminations needed
    • Input frequencies: 1MHz to 800MHz (250MHz for LVCMOS)
    • Reference monitor qualifies/disqualifies input clock
  • Programmable status output
  • 4 differential/8 LVCMOS outputs
    • Any frequency from 10MHz to 1GHz (180MHz for LVCMOS)
    • Programmable output buffer supports HCSL (DC-coupled), LVDS/LVPECL/CML (AC-coupled) or two LVCMOS
    • Differential output swing is selectable: 400mV to 800mV
    • Output clock phase individually adjustable in 100ps steps
    • Output Enable input with programmable effect
  • Supports up to 1MHz I2C or up to 20MHz SPI serial processor port
  • Can configure itself automatically after reset through internal customer-definable One-Time Programmable (OTP) memory with up to four different configurations
  • 4 × 4 mm 24-VFQFPN package

文档

文档标题 类型 日期
PDF2.80 MB
数据手册
PDF1.99 MB
应用文档
PDF377 KB
应用文档
PDF129 KB
应用文档
PDF256 KB
应用文档
PDF433 KB
应用文档
PDF353 KB
应用文档
PDF395 KB
应用文档
PDF170 KB
应用文档
PDF495 KB
应用文档
PDF442 KB
应用文档
PDF115 KB
应用文档
PDF233 KB
应用文档
PDF131 KB
应用文档
PDF180 KB
应用文档
PDF160 KB
应用文档
PDF120 KB
应用文档
PDF143 KB
应用文档
PDF565 KB
应用文档
PDF136 KB
应用文档
PDF202 KB
应用文档
PDF121 KB
应用文档
PDF438 KB
应用文档
PDF108 KB
应用文档
PDF80 KB
指南
PDF1.22 MB
手册 - 软件
XLSX482 KB
其他
PDF906 KB
概览
PDF1.83 MB
概览
PDF15.98 MB
报告
 

设计和开发

软件与工具

软件下载

文档标题 类型 日期
ZIP17.27 MB
软件和工具 - 软件
ZIP183.57 MB
软件和工具 - 软件
 

开发板与套件

开发板与套件

模型

模型

Title Type Date
ZIP28 KB
模型 - IBIS
 

支持

视频和培训

Lab on the Cloud Demo for Femtoclock®2 Ultra-Low Phase Noise Synthesizer and Jitter Attenuator

Demonstration of Renesas’ Lab on the Cloud virtual environment for Femtoclock®2 ultra-low phase noise synthesizer and jitter attenuator.