概览

描述

The 9ZML1252E is a second generation 2-input/12-output differential mux for Intel Purley and newer platforms. It exceeds the demanding DB1200ZL performance specifications and is backwards compatible to the 9ZML1232B. It utilizes Low Power HCSL-compatible outputs to reduce power consumption and termination resistors. It is suitable for PCI-Express Gen1-4 or QPI/UPI applications, and provides 2 configurable low-drift I2O settings, one for each input channel, to allow I2O tuning for various topologies.

特性

  • 2 configurable low-drift I2O delays up to 2.9ns; maintain transport delay for various topologies
  • LP-HCSL outputs with Zout = 85Ω; eliminate 48 resistors
  • 9 selectable SMBus addresses; multiple devices can share same SMBus segment
  • Separate VDDIO for outputs; allows maximum power savings
  • PLL or Bypass Mode; PLL can dejitter incoming clock
  • Hardware or software-selectable PLL BW; minimizes jitter peaking in downstream PLLs
  • Spread spectrum compatible; tracks spreading input clock for EMI reduction
  • SMBus interface; software can modify device settings without hardware changes
  • 10 x 10 mm 72-QFN package; small board footprint

应用

文档

文档标题 类型 日期
PDF382 KB
数据手册
PDF1.99 MB
应用文档
PDF244 KB
应用文档
PDF255 KB
应用文档
PDF322 KB
应用文档
PDF480 KB
应用文档
PDF235 KB
应用文档
PDF170 KB
应用文档
PDF495 KB
应用文档
PDF442 KB
应用文档
PDF565 KB
应用文档
PDF121 KB
应用文档
PDF137 KB
应用文档
PDF2.40 MB
概览
PDF1.83 MB
概览
PDF163 KB
产品变更通告
PDF158 KB
产品变更通告
PDF983 KB
产品变更通告

设计和开发

开发板与套件

开发板与套件

模块

支持

视频和培训

PCIe Gen5 Clock Buffers

Introducing Renesas’ enhanced PCIe clock buffer family. These PCIe Gen5 clock buffers offer fanout and zero-delay operating modes, supporting both legacy systems and the most complex timing trees within a single device. Unlike many existing solutions, whose performance limitations force their use in fanout buffer mode, these clock buffers meet both PCIe Gen5 and prominent CPU-specific phase jitter requirements in all operating modes. The extremely low 50fs rms PCIe Gen5 additive phase jitter enables multi-level cascading within the strict PCIe Gen5 jitter budget. Renesas’ high-performance oscillators and clock generators provide an ideal clock source for the enhanced PCIe clock buffer family. 

For more information about these PCIe Gen5 clock buffers, visit the PCIe timing page