The IDT8T33FS314I is a low skew 1-to-4 Differential Fanout Buffer, designed with clock distribution in mind, accepting two clock sources into an input MUX. The MUX is controlled by a CLK_SEL pin. This makes the IDT8T33FS314I very versatile, in that, it can operate as both a differential clock buffer as well as a signal-level translator and fanout buffer.

The device is designed on a SiGe process and can operate at frequencies in excess of 2.7GHz. This ensures negligible jitter introduction to the timing budget which makes it an ideal choice for distributing high frequency, high precision clocks across back planes and boards in communication systems. Internal temperature compensation guarantees consistent performance across various platforms.

特長

  • Four differential ECL/LVPECL level outputs
  • One differential ECL/LVPECL or single-ended input (CLKA)
    One differential HSTL or single-ended input (CLKB)
  • Maximum output frequency: 2.7GHz
  • Additive phase jitter, RMS: 0.114ps (typical) @ 156.25MHz
  • Output skew: 50ps (maximum)
  • LVPECL and HSTL mode operating voltage supply range:
    VCC = 2.5V±5% or 3.3V±5%, VEE = 0V
  • ECL mode operating voltage supply range:
    VEE = -3.3V±5% or -2.5V±5%, VCC = 0V
  • -40°C to 85°C ambient operating temperature
  • Lead-free (RoHS 6) packaging

製品選択

製品名 Part Status Pkg. Type Lead Count (#) Temp. Grade Pb (Lead) Free Carrier Type 購入/サンプル
Obsolete TSSOP 20 I はい Tube
Availability
Obsolete TSSOP 20 I はい Reel
Availability
Obsolete SSOP 20 I はい Tube
Availability
Obsolete SSOP 20 I はい Reel
Availability

ドキュメント&ダウンロード

タイトル language 分類 形式 サイズ 日付
データシート
8T33FS314I Data Sheet データシート PDF 825 KB
アプリケーションノート、ホワイトペーパー
AN-828 Termination - LVPECL アプリケーションノート PDF 322 KB
AN-844 Termination - AC Coupling Clock Receivers アプリケーションノート PDF 170 KB
AN-842 Thermal Considerations in Package Design and Selection アプリケーションノート PDF 495 KB
AN-840 Jitter Specifications for Timing Signals アプリケーションノート PDF 442 KB
AN-834 Hot-Swap Recommendations アプリケーションノート PDF 153 KB
AN-833 Differential Input Self Oscillation Prevention アプリケーションノート PDF 180 KB
AN-836 Differential Input to Accept Single-ended Levels アプリケーションノート PDF 120 KB
AN-835 Differential Input with VCMR being VIH Referenced アプリケーションノート PDF 160 KB
AN-827 Application Relevance of Clock Jitter アプリケーションノート PDF 1.15 MB
AN-815 Understanding Jitter Units アプリケーションノート PDF 565 KB
AN-805 Recommended Ferrite Beads アプリケーションノート PDF 121 KB
PCN / PDN
PDN#: CQ-19-04 Product Discontinuance Notice 製品中止通知 PDF 1010 KB
PCN# : A1809-02 Add Alternate Assembly Location on select Packages 製品変更通知 PDF 25 KB
PCN# : A1602-01(R1) Add Greatek Taiwan as Alternate Assembly 製品変更通知 PDF 611 KB
PCN# : A1602-01 Add Greatek Taiwan as Alternate Assembly 製品変更通知 PDF 611 KB
PCN# : A1511-01(R1) Add SPEL India as Alternate Assembly Location 製品変更通知 PDF 596 KB
PCN# : A1511-01 Add SPEL India as Alternate Assembly Location 製品変更通知 PDF 544 KB
PCN# : TB1503-01R1 Carrier Tape Standardization for Selective Packages 製品変更通知 PDF 333 KB
PCN# : TB1503-01 Carrier Tape Standardization for Selective Packages 製品変更通知 PDF 291 KB
その他資料
IDT Clock Distribution Overview (Japanese) English 概要 PDF 7.79 MB
IDT Clock Generation Overview (Japanese) English 概要 PDF 2.19 MB

ニュース&各種リソース