Single-Ended Fanout Buffers and Dividers by IDT

Description

Overview of IDT's single-ended fanout buffers and single-ended fanout dividers. Fanout buffers are a useful building block of many clock trees, providing signal buffering and multiple low-skew copies of the input signal. The clock fanout from a single input reduces loading on the preceding driver and provides an efficient clock distribution network. Presented by Vik Chaudhry, technical marketing manager at IDT. For more information about IDT's rich portfolio of clock IC timing solutions, visit www.idt.com/go/clocks.

 

Transcript

Thank you for joining us for an overview of IDTs Fanout Buffers. My name is Vik Chaudhry, I'm Marketing Manager for IDT's Timing Products.
 
Now, let's consider some single-ended Buffers. In this example we have a differential signal or a crystal input coming in that is fanned out to ten single-ended LVCMOS signals. Typically, the differential inputs can accept either LDVS, LVPECL, HCSL, or HSTL levels. 
 
This is an example of a very flexible device where one, we have a mux at the input stage, two, we have two sets of dividers that are independent of each other, and three, there are two sets of fanout buffers for each of the banks, with an able signal for each bank.
 
IDT has a very large portfolio of fanout and clock distribution devices. To make it easy to select these parts, we have developed the collateral that can be used. This collateral is located on the IDT website under our clock and timing products, and if you look under fanout buffers and dividers, you will see this collateral available.
 
We also have an excellent application support for all the clocks and clock distribution devices.  Most of our products include IBIS models, we also have application notes for various termination schemes, filter recommendations, and we also review schematics. If you have any questions, please feel free to either drop us an email at TSD-Applications@IDT.com or clocks@IDT.com.
 
Thank you for choosing IDT timing products.