Overview

Description

Along with CSPUA877A or 98ULPA877A DDR2 PLL Provides a fully JEDEC compliant solution for DDR2 RDIMMs for 400, 533, 667 and 800MHz.

Features

  • 25-bit 1:1 or 14-bit 1:2 configurable registered buffer with parity check functionality
  • Supports SSTL_18 JEDEC specification on data inputs and outputs
  • Supports LVCMOS switching levels on CSR and RESET inputs
  • Low voltage operation VDD = 1.7V to 1.9V

Comparison

Applications

Documentation

Type Title Date
Datasheet PDF 710 KB
End Of Life Notice PDF 938 KB
End Of Life Notice PDF 909 KB
Product Change Notice PDF 113 KB
Product Change Notice PDF 30 KB
Product Change Notice PDF 398 KB
6 items

Design & Development

Models