Along with CSPUA877A or 98ULPA877A DDR2 PLL Provides a fully JEDEC compliant solution for DDR2 RDIMMs for 400, 533, 667 and 800MHz.


  • 25-bit 1:1 or 14-bit 1:2 configurable registered buffer with parity check functionality
  • Supports SSTL_18 JEDEC specification on data inputs and outputs
  • Supports LVCMOS switching levels on CSR and RESET inputs
  • Low voltage operation VDD = 1.7V to 1.9V

tuneProduct Options

Part Number Part Status Pkg. Type Lead Count (#) Temp. Grade Pb (Lead) Free Carrier Type Buy Sample
Active CABGA 96 C Yes Tray
Active CABGA 96 C Yes Reel


Title language Type Format File Size Date
Datasheets & Errata
star 74SSTUBF32866B Datasheet Datasheet PDF 710 KB
PCN# : PCN20001 Add Alternate Substrate Supplier for Select CABGA and FCBGA Packages Product Change Notice PDF 113 KB
PCN# : A1609-02 Alternate Site at OSET Taiwan on Select Packages Product Change Notice PDF 30 KB
PCN#: A1309-03 Additional Assembly Sources Product Change Notice PDF 398 KB