The 8761I is a low voltage, low skew PCI / PCI-X clock generator. The 8761I has a selectable REF_CLK or crystal input. The REF_CLK input accepts LVCMOS or LVTTL input levels. The 8761I has a fully integrated PLL along with frequency configurable clock and feedback outputs for multiplying and regenerating clocks with "zero delay". Using a 20MHz or 25MHz crystal or a 33.333MHz or 66.666MHz reference frequency, the 8761I will generate output frequencies of 33.333MHz, 66.666MHz, 100MHz and 133.333MHz simultaneously. The low impedance LVCMOS/LVTTL outputs of the 8761I are designed to drive 50Ω series or parallel terminated transmission lines.

Features

  • Fully integrated PLL
  • Seventeen LVCMOS/LVTTL outputs, 15Ω typical output impedance
  • Selectable crystal oscillator interface or LVCMOS/LVTTL REF_CLK
  • Maximum output frequency: 166.67MHz
  • Maximum crystal input frequency: 40MHz
  • Maximum REF_CLK input frequency: 83.33MHz
  • Individual banks with selectable output dividers for generating 33.333MHz, 66.66MHz, 100MHz and 133.333MHz simultaneously
  • Separate feedback control for generating PCI / PCI-X frequencies from a 20MHz or 25MHz crystal or 33.333MHz or 66.666MHz reference frequency
  • Cycle-to-cycle jitter: 70ps (maximum)
  • Period jitter, RMS: 17ps (maximum)
  • Output skew: 250ps (maximum)
  • Bank skew: 50ps (maximum)
  • Static phase offset: 0 ± 150ps (maximum)
  • Full 3.3V or 3.3V core, 2.5V multiple output supply modes
  • -40°C to 85°C ambient operating temperature
  • Available in lead-free RoHS-compliant package

Product Options

Part Number Part Status Pkg. Type Lead Count (#) Temp. Grade Pb (Lead) Free Carrier Type Buy Sample
Obsolete TQFP 64 I Yes Tray
Availability
Obsolete TQFP 64 I Yes Reel
Availability

Documentation & Downloads

Title language Type Format File Size Date
Datasheets & Errata
8761i Datasheet Datasheet PDF 769 KB
Application Notes & White Papers
AN-828 Termination - LVPECL Application Note PDF 322 KB
AN-845 Termination - LVCMOS Application Note PDF 146 KB
AN-844 Termination - AC Coupling Clock Receivers Application Note PDF 170 KB
AN-842 Thermal Considerations in Package Design and Selection Application Note PDF 495 KB
AN-840 Jitter Specifications for Timing Signals Application Note PDF 442 KB
AN-834 Hot-Swap Recommendations Application Note PDF 153 KB
AN-836 Differential Input to Accept Single-ended Levels Application Note PDF 120 KB
AN-835 Differential Input with VCMR being VIH Referenced Application Note PDF 160 KB
AN-827 Application Relevance of Clock Jitter Application Note PDF 1.15 MB
AN-815 Understanding Jitter Units Application Note PDF 565 KB
AN-805 Recommended Ferrite Beads Application Note PDF 121 KB
PCNs & PDNs
PDN# : CQ-19-01(R1) Quarterly Market Declined PDN Product Discontinuation Notice PDF 1014 KB
PDN# : CQ-19-01 Quarterly Market Declined PDN Product Discontinuation Notice PDF 537 KB
PDN# : CQ-16-04 QUARTER MARKET DECLINED PDN Product Discontinuation Notice PDF 560 KB
PCN# : A1602-01(R1) Add Greatek Taiwan as Alternate Assembly Product Change Notice PDF 611 KB
PCN# : A1602-01 Add Greatek Taiwan as Alternate Assembly Product Change Notice PDF 611 KB
PDN# : N-12-22R2 PRODUCT DISCONTINUANCE NOTICE Product Discontinuation Notice PDF 363 KB
PDN# : N-12-22R1 PRODUCT DISCONTINUANCE NOTICE Product Discontinuation Notice PDF 209 KB
Downloads
8761I IBIS Model Model - IBIS ZIP 67 KB
Other
Clock Distribution Overview 日本語 Overview PDF 217 KB
IDT Clock Generation Overview 日本語 Overview PDF 1.83 MB