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Search has returned 27 results
Title Type Format File Size Language Date
AN-891 Driving LVPECL, LVDS, CML, and SSTL Logic with Universal Low-Power HCSL Outputs Application Note PDF 431 KB English
AN-805 Recommended Ferrite Beads Application Note PDF 91 KB English
Package Outline Drawing Package Code: NDG48P3 48-VFQFPN 6.0 x 6.0 x 0.9 mm Body, 0.4 mm Pitch Package Outline Drawing PDF 195 KB English
9ZXL04x1E-9ZXL06x1E-9ZXL08x1E-9ZXL12x1E Family Datasheet Datasheet PDF 474 KB English
Package Outline Drawing Package Code: NDG48P1 48-VFQFPN 6.0 x 6.0 x 0.9 mm Body, 0.4 mm Pitch Package Outline Drawing PDF 193 KB English
PCN# : 220015 (R1) Add Alternate Assembly Location on VFQFPN Packages Product Change Notice PDF 734 KB English
PCN# : 220015 Add Alternate Assembly Location on VFQFPN Packages Product Change Notice PDF 728 KB English
AN-827 Application Relevance of Clock Jitter Application Note PDF 1.99 MB English
Package Outline Drawing Package Code: NDG48P5 48-VFQFPN 6 x 6 x 0.9 mm Body, 0.4mm Pitch Package Outline Drawing PDF 197 KB English
PCN# : A1904-01 Add Greatek, Taiwan as an Alternate Assembly Facility Product Change Notice PDF 983 KB English
Package Outline Drawing Package Code: NDG48P4 48-VFQFPN 6.0 x 6.0 x 0.9 mm Body, 0.4 mm Pitch Package Outline Drawing PDF 193 KB English
Package Outline Drawing Package Code: NDG48S1 48-VFQFPN 6.0 x 6.0 x 0.9 mm Body, 0.4 mm Pitch Package Outline Drawing PDF 198 KB English
48-VFQFPN Package Outline Drawing 6.0 x 6.0 x 0.90 mm Body, Epad 4.1 x 4.1 mm, 0.40mm Pitch NDG48P1 Package Outline Drawing PDF 130 KB English
Package Outline Drawing Package Code: NDG48P2 48-VFQFPN 6.0 x 6.0 x 0.9 mm Body, 0.4mm Pitch Package Outline Drawing PDF 192 KB English
Green Products RoHS Material Declaration Certificate Certificate PDF 170 KB English
9ZXL0831E IBIS Model Model - IBIS ZIP 20 KB English
AN-1001 Combining PhiClock and 9ZXL1951D for PCIe Gen4/5 Application Note PDF 244 KB English
AN-975 Cascading PLLs Application Note PDF 255 KB English
AN-828 Termination - LVPECL Application Note PDF 322 KB English
AN-879 Low-Power HCSL vs Traditional HCSL Application Note PDF 235 KB English
AN-844 Termination - AC Coupling Clock Receivers Application Note PDF 170 KB English
AN-842 Thermal Considerations in Package Design and Selection Application Note PDF 495 KB English
AN-840 Jitter Specifications for Timing Signals Application Note PDF 442 KB English
AN-835 Differential Input with VCMR being VIH Referenced Application Note PDF 160 KB English
AN-836 Differential Input to Accept Single-ended Levels Application Note PDF 120 KB English
AN-815 Understanding Jitter Units Application Note PDF 565 KB English
AN-808 PCI Express/HCSL Termination Application Note PDF 137 KB English