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Search has returned 27 results
Title Type Format File Size Language Date
Package Outline Drawing Package Code: NDG20P1 20-VFQPFN 3.0 x 3.0 x 0.9 mm Body, 0.4mm Pitch Package Outline Drawing PDF 193 KB English
Timing Commander Installer (v1.17) Software & Tools - Software ZIP 18.02 MB English
VersaClock 3S Timing Commander Personality File (v.1.5.1) Software & Tools - Other ZIP 5.84 MB English
AN-891 Driving LVPECL, LVDS, CML, and SSTL Logic with Universal Low-Power HCSL Outputs Application Note PDF 431 KB English
Termination Options for High-Speed LVCMOS Driver Clock Drivers Application Note PDF 187 KB English
Timing Commander Installation Guide Application Note PDF 348 KB English
VersaClock Family Overview Overview PDF 392 KB English
PCB Layout Considerations for Designing VersaClock Clock Generator Family Application Note PDF 1.17 MB English
NDG20 Package Outline Drawing 3.0 X 3.0 mm Body, 0.40mm Pitch VFQFPN Package Outline Drawing PDF 179 KB English
How to Make 1.2V LVCMOS from 1.8V LVCMOS Output Application Note PDF 256 KB English
PCN# : TB1912-02(R1) Convert Shipping Media from Tube or Tray to Cut Reel Product Change Notice PDF 5.71 MB English
PCN# : TB1912-02 Convert Shipping Media from Tube or Tray to Cut Reel Product Change Notice PDF 5.61 MB English
PCN# : TP1910-01 VBAT Power Domain Required Product Change Notice PDF 110 KB English
5L35021 Datasheet Datasheet PDF 620 KB English
20-VFQFPN Package Outline Drawing 3.0 x 3.0 x 0.90 mm, 0.40mm Pitch, 1.65 x 1.65 mm Epad, Wettable Flank NDG20S2 Package Outline Drawing PDF 202 KB English
20-VFQFPN Package Outline Drawing 3.0 x 3.0 x 0.90 mm, 0.40mm Pitch, 1.65 x 1.65 mm Epad,Wettable Flank NDG20S1 Package Outline Drawing PDF 195 KB English
Package Outline Drawing Package Code:NDG20P2 20-VFQFPN 3.0 x 3.0 x 0.9 mm, 0.4mm Pitch Package Outline Drawing PDF 193 KB English
Green Products RoHS Material Declaration Certificate Certificate PDF 170 KB English
5L35021 IBIS Model Model - IBIS ZIP 27 KB English
AN-918 Programmable Clocks vs Crystal Oscillators Application Note PDF 307 KB English
IDT Clocks for Altera's Stratix V and Arria V/X FPGAs Technical Brief PDF 238 KB English
AN-844 Termination - AC Coupling Clock Receivers Application Note PDF 170 KB English
AN-846 Termination - LVDS Application Note PDF 133 KB English
AN-842 Thermal Considerations in Package Design and Selection Application Note PDF 495 KB English
AN-815 Understanding Jitter Units Application Note PDF 565 KB English
AN-808 PCI Express/HCSL Termination Application Note PDF 137 KB English
AN-806 Power Supply Noise Rejection Application Note PDF 438 KB English