The 852911I is a low skew, 1-to-9 Differential-to-HSTL Fanout Buffer. The 852911I has two selectable clock inputs which can accept most differential input levels.

Guaranteed output skew, part-to-part skew and crossover voltage characteristics make the 852911I ideal for today’s most advanced applications, such as IA64 and static RAMs.

特性

  • 9 HSTL outputs
  • Selectable differential CLK, nCLK or LVPECL clock inputs
  • HSTL_CLK, nHSTL_CLK pair can accept the following differential input levels:
    LVPECL, LVDS, HSTL, SSTL, HCSL
  • PECL_CLK, nPECL_CLK supports the following input types:
    LVPECL, CML, SSTL
  • Maximum output frequency: 500MHz
  • Output skew: 100ps (maximum)
  • Part-to-part skew: 300ps (maximum)
  • Propagation delay: 1.7ns (maximum)
  • VOH = 1.4V (maximum)
  • 3.3V core, 1.6V to 3.6V output supply range
  • -40°C to 85°C ambient operating temperature​

description文档

文档标题 language 类型 文档格式 文件大小 日期
数据手册与勘误表
star 852911i Datasheet 数据手册 PDF 256 KB
应用指南 & 白皮书
AN-828 Termination - LVPECL 应用文档 PDF 322 KB
AN-844 Termination - AC Coupling Clock Receivers 应用文档 PDF 170 KB
AN-842 Thermal Considerations in Package Design and Selection 应用文档 PDF 495 KB
AN-840 Jitter Specifications for Timing Signals 应用文档 PDF 442 KB
AN-833 Differential Input Self Oscillation Prevention 应用文档 PDF 180 KB
AN-834 Hot-Swap Recommendations 应用文档 PDF 153 KB
AN-835 Differential Input with VCMR being VIH Referenced 应用文档 PDF 160 KB
AN-836 Differential Input to Accept Single-ended Levels 应用文档 PDF 120 KB
AN-815 Understanding Jitter Units 应用文档 PDF 565 KB
AN-827 Application Relevance of Clock Jitter 应用文档 PDF 1.15 MB
AN-805 Recommended Ferrite Beads 应用文档 PDF 121 KB
PCN / PDN
PDN# : CQ-19-01(R1) Quarterly Market Declined PDN 产品停产通告 PDF 1014 KB
PDN# : CQ-19-01 Quarterly Market Declined PDN 产品停产通告 PDF 537 KB
其他
Clock Distribution Overview 概览 PDF 217 KB
IDT Clock Generation Overview 概览 PDF 1.83 MB

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