概览

描述

The 9ZXL1231E is a second-generation, enhanced performance DB1200ZL differential buffer. The part is a pin-compatible upgrade to the 9ZXL1231A, while offering much improved phase jitter performance and increased system security features. A fixed external feedback maintains low drift for critical QPI/UPI applications.

特性

  • LP-HCSL outputs; eliminate 24 resistors, save 41mm² of area
  • PCIe Gen 1–5 compliance
  • 12 OE# pins; hardware control of each output
  • 9 selectable SMBus addresses; multiple devices can share the same SMBus segment
  • Selectable PLL BW; minimizes jitter peaking in cascaded PLL topologies
  • Hardware/SMBus control of PLL bandwidth and bypass; change mode without power cycle
  • Spread spectrum compatible; tracks spreading input clock for EMI reduction
  • 100MHz and 133.33MHz PLL Mode; UPI and legacy QPI support
  • 9 x 9 mm 64-VFQFPN package; small board footprint

应用

文档

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产品变更通告

设计和开发

开发板与套件

开发板与套件

模块

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视频和培训

PCIe Gen5 Clock Buffers

Introducing Renesas’ enhanced PCIe clock buffer family. These PCIe Gen5 clock buffers offer fanout and zero-delay operating modes, supporting both legacy systems and the most complex timing trees within a single device. Unlike many existing solutions, whose performance limitations force their use in fanout buffer mode, these clock buffers meet both PCIe Gen5 and prominent CPU-specific phase jitter requirements in all operating modes. The extremely low 50fs rms PCIe Gen5 additive phase jitter enables multi-level cascading within the strict PCIe Gen5 jitter budget. Renesas’ high-performance oscillators and clock generators provide an ideal clock source for the enhanced PCIe clock buffer family. 

For more information about these PCIe Gen5 clock buffers, visit the PCIe timing page