The ADC1215S is a single-channel 12-bit Analog-to-Digital Converter (ADC) optimized for high dynamic performances and low power consumption at sample rates up to 105 Msps. Pipelined architecture and output error correction ensure the ADC1215S is accurate enough to guarantee zero missing codes over the entire operating range. Supplied from a single 3 V source, it can handle output logic levels from 1.8 V to 3.3 V in CMOS mode. It supports the LVDS DDR output standard. An integrated SPI allows the user to easily configure the ADC. With excellent dynamic performance from the baseband to input frequencies of 170 MHz or more. The integrated input buffer ensures that the input impedance remains constant and low and the performance consistent over a wide frequency range.

特性

  • 12-bit pipelined ADC core
  • Clock input divider by 2 for less jitter contribution
  • CMOS or LVDS DDR digital outputs
  • Duty cycle stabilizer
  • Fast OuT of Range (OTR) detection
  • Flexible input voltage range: 1 V p-p to 2 V p-p
  • HVQFN40 package
  • Input bandwidth, 600 MHz
  • Integrated input buffer
  • Offset binary, 2's complement, gray code
  • Pin compatible with the ADC1415S series, ADC1115S series and the ADC1015S
  • series
  • Power-down and Sleep modes
  • Sample rate up to 105 Msps
  • Serial Peripheral Interface (SPI)
  • SNR, 70.5 dBFS
  • SFDR, 90 dBc

产品选择

器件号 Part Status Pkg. Type Lead Count (#) Temp. Grade Pb (Lead) Free Carrier Type Buy Sample
ADC1215S105HN-C1
Obsolete VFQFPN 40 I 是的 Tray
Availability
ADC1215S105HN-C18
Obsolete VFQFPN 40 I 是的 Reel
Availability

文档和下载

文档标题 其他语言 类型 文档格式 文件大小 日期
数据手册与勘误表
ADC1215S SER Datasheet 数据手册 PDF 377 KB
PCN / PDN
PDN# : DC-14-01 PRODUCT DISCONTINUANCE NOTICE 产品停产通告 PDF 538 KB

开发板与套件

器件号 文档标题 类型 Company
ADC1215S105F1 ADC1215S105F1 demo board; CMOS version; SPI, Regulators and CMOS buffer on board 演示 Renesas
ADC1215S105F2 ADC1215S105F2 demo board; SPI, Regulators on board; LVDS output only SAMTEC connector 演示 Renesas