Use this form to upload your Timing Commander configuration file for the 5P1103 part. This will disable the configurator below. The datasheet addendum will be provided by Renesas after review.
Configuration File (.tcs) Uploader
Selects output type of Output x. Available options are differential signalling (LVDS, LVPECL, HCSL) or single-ended (LVCMOS: first output of bank active, second output of bank active, or both outputs active either in phase or 180 degrees out of phase).
Note: HCSL and LVPECL outputs support a VDDO Voltage of 2.5 V or 3.3 V only. Selects output type of Output x. Available options are differential signalling (LVDS, LVPECL, HCSL) or single-ended (LVCMOS: first output of bank active, second output of bank active, or both outputs active either in phase or 180 degrees out of phase).
Power supply voltage (VDDO) of output. Determines the output signal's high and low voltages.
Note: 1.8 V is not compatible with HCSL or LVPECL Output Type. Power supply voltage (VDDO) of output x. Determines the output signal's high and low voltages.
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