The 85356I is a dual 2:1 Differential-to-LVPECL Multiplexer. The device has both common select and individual select inputs. When COM_SEL is logic High, the CLKxx input pairs will be passed to the output. When COM_SEL is logic Low, the output is determined by the setting of the SEL0 pin for channel 0 and the SEL1 pin for Channel 1. The differential input has a common mode range that can accept most differential input types such as LVPECL, LVDS, LVHSTL, SSTL, and HCSL. The 85356I can therefore be used as a differential translator to translate almost any differential input type to LVPECL. It can also be used in ECL mode by setting VCC = 0V and VEE to -3.0V to - 3.8V. The 85356I adds negligible jitter to the input clock and can operate at high frequencies in excess of 900MHz thus making it ideal for use in demanding applications such as SONET, Fibre Channel, 1 Gigabit/10 Gigabit Ethernet.

特長

  • High speed differential muliplexer. The device can be configured as a 2:1 multiplexer
  • Dual 3.3V LVPECL outputs
  • Selectable differential CLKx/nCLKx input pairs
  • Differential CLKx/nCLKx pairs can accept the following interface levels: LVPECL, LVDS, LVHSTL, HCSL, SSTL
  • Output frequency: 900MHz (typical)
  • Translates any single-ended input signal to 3.3V LVPECL levels with resistor bias on nCLKx input
  • Output skew: 75ps (typical)
  • Propagation delay: 1.15ns (typical)
  • LVPECL mode operating voltage supply range: VCC = 3V to 3.8V, VEE = 0V
  • ECL mode operating voltage supply range: VCC = 0V, VEE = -3V to -3.8V
  • -40°C to 85°C ambient operating temperature
  • Available in lead-free (RoHS 6) package

製品選択

製品名 Part Status Pkg. Type Lead Count (#) Temp. Grade Pb (Lead) Free Carrier Type 購入/サンプル
85356AGILF
Obsolete TSSOP 20 I はい Tube
Availability
85356AGILFT
Obsolete TSSOP 20 I はい Reel
Availability
85356AMILF
Obsolete SOIC 20 I はい Tube
Availability
85356AMILFT
Obsolete SOIC 20 I はい Reel
Availability

ドキュメント&ダウンロード

タイトル 他の言語 分類 形式 サイズ 日付
データシート
85356I Datasheet データシート PDF 699 KB
アプリケーションノート、ホワイトペーパー
AN-828 Termination - LVPECL アプリケーションノート PDF 322 KB
AN-844 Termination - AC Coupling Clock Receivers アプリケーションノート PDF 170 KB
AN-842 Thermal Considerations in Package Design and Selection アプリケーションノート PDF 495 KB
AN-840 Jitter Specifications for Timing Signals アプリケーションノート PDF 442 KB
AN-838 Peak-to-Peak Jitter Calculations アプリケーションノート PDF 115 KB
AN-839 RMS Phase Jitter アプリケーションノート PDF 233 KB
AN-833 Differential Input Self Oscillation Prevention アプリケーションノート PDF 180 KB
AN-834 Hot-Swap Recommendations アプリケーションノート PDF 153 KB
AN-836 Differential Input to Accept Single-ended Levels アプリケーションノート PDF 120 KB
AN-835 Differential Input with VCMR being VIH Referenced アプリケーションノート PDF 160 KB
AN-827 Application Relevance of Clock Jitter アプリケーションノート PDF 1.15 MB
AN-815 Understanding Jitter Units アプリケーションノート PDF 565 KB
AN-805 Recommended Ferrite Beads アプリケーションノート PDF 121 KB
PCN / PDN
PDN# : CQ-19-01(R1) Quarterly Market Declined PDN 製品中止通知 PDF 1014 KB
PDN# : CQ-19-01 Quarterly Market Declined PDN 製品中止通知 PDF 537 KB
PCN# : A1602-01(R1) Add Greatek Taiwan as Alternate Assembly 製品変更通知 PDF 611 KB
PCN# : A1602-01 Add Greatek Taiwan as Alternate Assembly 製品変更通知 PDF 611 KB
PCN# : A1511-01(R1) Add SPEL India as Alternate Assembly Location 製品変更通知 PDF 596 KB
PCN# : A1511-01 Add SPEL India as Alternate Assembly Location 製品変更通知 PDF 544 KB
PCN# : TB1504-01R1 Qty per Reel Standardization for Selective Packages 製品変更通知 PDF 95 KB
PCN# : TB1504-01 Qty per Reel Standardization for Selective Packages 製品変更通知 PDF 50 KB
PCN# : TB1303-02 Change of Tape & Reel Packing Method for Selective Products 製品変更通知 PDF 361 KB
ダウンロード
85356I IBIS Model モデル-IBIS ZIP 35 KB
その他資料
IDT Clock Distribution Overview (Japanese) English 概要 PDF 7.79 MB
IDT Clock Generation Overview (Japanese) English 概要 PDF 2.19 MB

ニュース&各種リソース