The 8S58035I is a high speed 2-to-6 Differential-to-LVPECL Fanout Buffer. The 8S58035I is optimized for high speed and very low output skew, making it suitable for use in demanding applications such as SONET, 1 Gigabit and 10 Gigabit Ethernet, and Fiber Channel. The internally terminated differential inputs and VREF_AC pins allow other differential signal families such as LVDS, LVDS and CML to be easily interfaced to the input with minimal use of external components. The device also has a 2:1 MUX input, allowing for easy selection between two clock reference sources. The 8S58035I is packaged in a small 5mm x 5mm 32-pin VFQFN package which makes it ideal for use in space-constrained applications.


  • Six LVPECL outputs
  • INx, nINx inputs can accept the following differential input levels:
  • 50Ω internal input termination to VT
  • Two selectable differential input pairs
  • Maximum output frequency: 3.2GHz
  • Output Skew: 45ps (maximum)
  • Part-to-Part Skew: 200ps (maximum)
  • Additive phase jitter, RMS: 47fs (typical),
    (fREF = 622.08MHz, 12kHz - 20MHz, VCC = 3.3V)
  • Propagation Delay: 580ps (maximum)
  • LVPECL mode operating voltage supply range:
    VCC = 2.5V±5%, 3.3V±10%, VEE = 0V
  • -40°C to 85°C ambient operating temperature​


製品名 Part Status Pkg. Type Lead Count (#) Temp. Grade Pb (Lead) Free Carrier Type 購入/サンプル
Active VFQFPN 32 I はい Tray
Active VFQFPN 32 I はい Reel


タイトル language 分類 形式 サイズ 日付
ICS8S58035I Datasheet データシート PDF 548 KB
AN-828 Termination - LVPECL アプリケーションノート PDF 322 KB
AN-844 Termination - AC Coupling Clock Receivers アプリケーションノート PDF 170 KB
AN-842 Thermal Considerations in Package Design and Selection アプリケーションノート PDF 495 KB
AN-840 Jitter Specifications for Timing Signals アプリケーションノート PDF 442 KB
AN-834 Hot-Swap Recommendations アプリケーションノート PDF 153 KB
AN-833 Differential Input Self Oscillation Prevention アプリケーションノート PDF 180 KB
AN-836 Differential Input to Accept Single-ended Levels アプリケーションノート PDF 120 KB
AN-835 Differential Input with VCMR being VIH Referenced アプリケーションノート PDF 160 KB
AN-827 Application Relevance of Clock Jitter アプリケーションノート PDF 1.15 MB
AN-815 Understanding Jitter Units アプリケーションノート PDF 565 KB
AN-805 Recommended Ferrite Beads アプリケーションノート PDF 121 KB
PCN# : A1904-01 Add Greatek, Taiwan as an Alternate Assembly Facility 製品変更通知 PDF 983 KB
PCN# : A1611-02 Add JCET China as Alternate Assembly and Change of Material Set at Alternate Assembly Location 製品変更通知 PDF 583 KB
PCN# : A1511-01(R1) Add SPEL India as Alternate Assembly Location 製品変更通知 PDF 596 KB
PCN# : A1511-01 Add SPEL India as Alternate Assembly Location 製品変更通知 PDF 544 KB
IDT Clock Distribution Overview (Japanese) English 概要 PDF 7.79 MB
IDT Clock Generation Overview (Japanese) English 概要 PDF 2.19 MB