RZ/A1LU is a cost-effective part in the RZ/A1 family with an Arm® Cortex®-A9 core running at 400MHz and 3MB of on-chip SRAM to support frame-buffers on-chip.


With 3MB on-chip SRAM, the RZ/A1LU supports up to 2 Displays with WVGA (800x480) resolution or a single display with WSVGA (1024x600) resolution without the need for external memory. RZ/A1LU enables very compact embedded designs without the need to worry about memory procurement and memory EOL. With RZ/A1LU, you can design your embedded system like an MCU and get the performance of a 400MHz Arm® Cortex®-A9 MPU. Enabled for support with Linux, RTOS or Bare-metal, this is the ideal device for designing Intelligent IoT End Point devices with compactness and high performance. Supported in QFP and BGA packages with different sizes to support board layout flexibility and with SDRAM interface to expand up to 128MB of external memory.

Get Started Using RZ/A1 MPUs


Key Features:

Part name/use/ package
176 pin    R7S721030VLFP
Car Accessory
176-pinQFP (24mm×24mm) 0.5mm pitch
Industry usage etc.
176-pinQFP (24mm×24mm) 0.5mm pitch
Industry usage etc.
176-pinBGA (8mm×8mm) 0.5mm pitch
208 pin R7S721031VLFP
Car Accessory
208-pinQFP (28mm×28mm) 0.5mm pitch
Industry usage etc.
208-pinQFP (28mm×28mm) 0.5mm pitch
233 pin R7S721031VLBG
Car Accessory
233-pinBGA (15mm×15mm) 0.8mm pitch
Industry usage etc.
233-pinBGA (15mm×15mm) 0.8mm pitch
Power supply voltage 3.3V/1.18V
Maximum operating frequency 400MHz
CPU core Arm® Cortex®-A9 (with Jazelle and NEON)
On-chip RAM Large-capacity memory: 3 MB
(For video display/work area; 128 KB are shared with data retention)
Cache memory Primary cache memory: 64 KB (separated 32K instruction/32K data, TLB128 entry) Secondary cache memory: 128 KB (with CoreLink™ Level 2 Cache Controller L2C-310)
External memory Bus clock: up to 66.67 MHz
Direct connection to SRAM, byte select SRAM, SDRAM, and  burst ROM (clock synchronous/clock asynchronous) using bus state controller. Address/data multiplexer I/O (MPX) interface supported.
Address space: 64 MB × 6
Data bus width: external 8/16/32 bits
Graphics functions Video display controller (1 channel of video input and 1 channel of panel output)
Capture engine unit (CMOS camera interface)
JPEG codec unit
Audio functions SCUX (with built-in asynchronous sampling rate conversion, digital volume & mute, and mixer function)
Serial sound interface × 4 channels
Renesas SPDIF interface
Timer functions Multifunction 16-bit timer (MTU2) × 5 channels
32-bit OS timer × 2 channels
Watchdog timer
Real-time clock
Connectivity functions USB 2.0 host/function module × 2 channels (host or functon selectable)
SD host interface × 2 channels (must obtain SD card license)
MMC host interface
Ethernet controller (10 Mbps/100 Mbps transfer, IEEE802.3 PHY interface MII)
Ethernet AVB(IEEE802.1 Audio/Video Bridging)Controller(requires nondisclosure agreement)
SPI multi I/O bus controller × 1 channel (up to 2 serial flash memory connectable to 1 channel, direct execution from CPU supported)
Serial communication interface with 16-stage FIFO (SCIF) × 5 channels (asynchronous and clock synchronous serial communication possible)
Serial communication interface × 2 channels (smart card interface, IrDA 1.0)
Renesas serial peripheral interface × 3 channels
I²C bus interface × 4 channels
Controller area network (CAN) × 2 channels
System analog functions Clock pulse generator (CPG): built-in PLL, maximum 32 times multiplication, built-in SSCG circuit
Direct memory access controller × 16 channels
Interrupt controller (with Arm® Generic Interrupt Controller [PL390])
A/D converter (12-bit resolution) × 8 channels
Debugging interface
CoreSight™ architecture
JTAG standard pin layout
Boot modes Boot mode 0: Boot from memory connected to CS0 space (16-bit bus)
Boot mode 1: Boot from serial flash memory
Boot mode 2: Boot from built-in NAND flash memory of SD controller
Boot mode 3: Boot from built-in NAND flash memory of MMC controller
Power-down modes Sleep mode
Software standby mode
Deep standby mode
Module standby mode

Pin Count / Memory Size Lineup:




Block Diagram:

Red font : Indication of different specifications between RZ/A1LU and RZ/A1L

Block diagram

*Arm, Cortex, CoreLink, and CoreSight are registered trademarks or trademarks of Arm Limited. 
OpenVG is a trademark of the Khronos Group. 
CAN (Controller Area Network): An automotive network specification developed by Robert Bosch GmbH of Germany. 
All other names of products or services mentioned here are trademarks or registered trademarks of their respective owners.

You can find an explanation of orderable part numbers here.


Resources for Software and Hardware

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Resources for Software and Hardware

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e2 studio Renesas eclipse embedded studio, known as e² studio, is a complete development and debug environment based on the popular Eclipse CDT project.


Hardware Design Support

Title Description
Oscillation circuit characteristics
Please search for your resonator on its manufacturer's site linked below. If you require optimal oscillation circuit constants for your particular system, please ask the manufacturer of the oscillator.

For main clock resonators:
Kyocera: Click for oscillation evaluation result.
Murata Manufacturing: For IC Manufacturer, select Renesas Electronics, and enter "R7S72103" into the IC Part Number search box.
Circuit CAD data, board CAD data Circuit diagram CAD data and substrate CAD data are offered. Please use it by all means.
You can filter the sample codes and application notes that are displayed using the below filters.

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