The 9ZXL1951D is a second-generation, enhanced performance DB1900ZL derivative buffer. The part is a pin-compatible upgrade to the 9ZXL1951A, offering a much improved phase jitter performance. It has 8 OE# pins that can be configured via SMBus to control up to 16 of the device's 19 outputs, and is packaged in a 6 x 6 mm QFN package for maximum space savings. A fixed external feedback maintains low drift for critical QPI/UPI applications.
Features
- LP-HCSL outputs with 85Ω Zout; eliminates 76 termination resistors, saves 130mm² area
- PCIe Gen 1–5 compliance
- 8 OE# pins configurable to control up to 16 outputs; easy power management
- 9 selectable SMBus addresses; multiple devices can share same SMBus segment
- Selectable PLL BW; minimizes jitter peaking in cascaded PLL topologies
- Hardware/SMBus control of PLL bandwidth and bypass; change mode without power cycle
- Spread spectrum compatible; tracks spreading input clock for EMI reduction
- 100MHz PLL mode; UPI support
- DIF input and DIF outputs on outer row of pins; easy board routing
- 6 x 6 mm dual-row 80-GQFN; smallest 19-output Z-buffer