The 9DB106 zero-delay buffer supports PCIe Gen1 and Gen2 clocking requirements. The 9DB106 is driven by a differential SRC output pair from an IDT CK410/CK505-compliant main clock generator. It attenuates jitter on the input clock and has a selectable PLL bandwidth to maximize performance in systems with or without Spread-Spectrum clocking. An SMBus interface allows control of the PLL bandwidth and bypass options, while 2 clock request (CLKREQ#) pins make the 9DB106 suitable for Express Card applications.
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Pkg. Type |
Lead Count (#) |
Temp. Grade |
Pb (Lead) Free |
Carrier Type |
Moisture Sensitivity Level (MSL) |
Price (USD) | 1ku |
Buy / Sample |
|
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Part Number | ||||||||
9DB106BGILF circleActive Samples Available |
TSSOP | 28 | I | Yes | Tube | 1 | 3.026 | Get Samples, |
TSSOP | 28 | I | Yes | Reel | 1 | 3.026 | ||
9DB106BGLF circleActive Samples Available |
TSSOP | 28 | C | Yes | Tube | 1 | 3.102 | Get Samples, |
TSSOP | 28 | C | Yes | Reel | 1 |