Renesas Advanced Technology: Packaging and System Assembly Technology

Technology: 2 of 2

―Renesas System Assembly Technology―Packaging and System Assembly Technology Enables Faster, Smaller, Lower-Power Circuitry

At Renesas, we are continuously working on ways to raise the value of our customers’ products. When it comes to system assembly technologies, we actively seek optimal designs involving all three mount stages: the inside of the package, the outside of the package, and the board itself. In particular, we work closely with our customers to anticipate and take actions to forestall potential problems, and we draw on deep experience to propose solutions. By taking this approach, we successfully produce robust semiconductor devices that stand up to challenging environments, and that will fully support the higher communication speeds that are coming to the industry.

Optimal Packaging Enables Better Performance

Packaging technologies are an essential part of the semiconductor manufacturing process. Most people are aware that technologists in this field are concerned with the design of semiconductor packages; but it is important to note that these technologists must also take into account the design of the chips that go into the package, and the design of the boards on which the packages are mounted.

Until recently, design work was clearly divided: the semiconductor manufacturer handled the design and manufacture of the chips and packages, while the customer designed the printed circuit boards. This approach, however, is no longer sufficient to fully exploit the performance possibilities enabled by the extremely high operating speeds that are quickly becoming standard. At Renesas, therefore, we work closely with board designers and board makers toward the goal of achieving optimal designs that cover all stages of mounting (Figure 1).

Figure 1: Renesas design scope extends beyond chips and packaging. We also work with customers toward optimal board design.

Figure 1: Renesas design scope extends beyond chips and packaging. We also work with customers toward optimal board design.

Packaging technologists face numerous challenges; they strive to achieve high densities, while overcoming obstacles such as heat generation, electromagnetic interference, and other operational stresses. These high densities also generate considerable heat; if the design does not limit and dissipate this heat appropriately, the overheating that results will lead to both temporary operational errors and permanent physical damage. As a result, countermeasures against the heat generation are very important. Also, in today’s state-of-the-art packages, there are a lot of areas where GHz-class signals flow, necessitating great attention to the problem of electromagnetic interference across signal lines. They remain as a major challenge to achieve higher densities and greater miniaturization.

Designers must therefore meet a wide range of requirements related to both thermal and mechanical stresses. Packaging technologists, therefore, must concern themselves with a very wide scope of parameters and its comprehensive optimization is required.

As an IDM, We Know About Stress

As a deeply experienced integrated design manufacturer (IDM), Renesas knows how to collaborate closely with customers as we design both our chips and our packaging solutions. For example, we begin working out thermal countermeasures starting from the very first stages of design, based on a careful consideration of the final product’s usage requirements. This proactive approach is considerably more cost-effective and time-efficient than the alternative—which is to wait until the board or enclosure is completed before starting to address these issues. That’s why we start by analyzing the structure and thermal characteristics of the anticipated target product, after which we develop chip designs and package structures that both limit and dissipate heat as required. Because our semiconductors are used in a vast range of products—in mobile devices, industrial machinery, automobiles, and much more—we are familiar with thermal and mechanical stress issues in many different environments, and we develop our technologies to meet the needs of each application. We excel at this type of approach because we draw on deep expertise in both chip and mount design, and because our advanced mount technologies enable us to collaborate meaningfully with our customers.

We Start Working with Customers at the Very Start of Product Conception

In recent years, our customers have faced growing issues with jitter, crosstalk, and electromagnetic compatibility (EMC). When circuits run at very high speed, for example, it is best to start approaching these issues at the chip design stage, rather than waiting to correct them by modifying the board patterns. This is why we start working with our customers during the initial product conception phase. We utilize sophisticated techniques, such as electromagnetic simulations and electromagnetic field imaging; and we apply comprehensive optimization to all stages of the design: semiconductor circuit design and layout, packaging design, and board layout.

As an example of our comprehensive optimization approach, refer to Figure 2. The conventional chip-oriented design (at left) is plagued by noise caused by a concentration of return current. By employing an approach that optimizes all three stages—the chips, the packages, and the board—we have corrected the problem by dispersing the return current, as shown at the right.

Figure 2: Benefits of Comprehensive Design

Figure 2: Benefits of Comprehensive Design

Packaging Technologies for Speeds Surpassing 10 Gbps

Finally, let’s take a brief look at leading-edge packaging techniques designed for high-performance products. Today’s newest network controllers operate at speeds above 10 Gbps, with high-speed signals moving from the board’s circuitry through the package contacts and into the chip. One well-known problem in achieving proper flow in these designs is impedance mismatch: if the impedance in the board circuitry does not match the impedance in the contacts on the package and chip, the signal tends to reflect back from the point where the impedance changes; this in turn corrupts the waveform and prevents accurate signal transmission. In the past, this problem was solved by adding corrective circuitry on the chip, or be incorporating passive elements within the package. Both methods, however, adversely impact on chip size and noise tolerance, and ultimately limit the achievable operating speed.

At Renesas, therefore, we take a different approach: we correct for impedance mismatch by placing through-holes through stacked substrates in the package—a technical measure that cancels out the reflected waves (see Fig. 3). This new approach allows us to achieve triple the conventional circuit density (as compared to conventionally designed Renesas implementations). This solution not only supports today’s high-speed products (at up to 12.5 Gpbs); it will also support the 16-Gbps communication speed established by PCI Express 4.0, as well as even faster 25-Gbps backbone networks.

Figure 3: Package Design Reduces Signal Degradation Caused by Impedance Mismatch

Figure 3: Package design reduces signal degradation caused by impedance mismatch

Also see related news release:

Renesas Electronics Develops Packaging Technology that Achieves Signal Transmission at Over 12.5 Gbps with Three Times Previous Levels of Signal Wiring Density

So as we have seen, Renesas system assembly technologies are helping to drive technical advances in or customers’ products. As a result, our customers are able to achieve higher performance, greater miniaturization, lower power consumption, and lower production costs. And these assembly technologies—as important as they are—are just one of the areas where we continue to find and implement solutions to support the many and varied needs of our customers.