Overview

MC100ES6226 is designed for very skew critical differential clock distribution systems and supports clock frequencies from DC up to 3.0 GHz. Typical applications for the MC100ES6226 are primary clock distribution systems on backplanes of high-performance computer, networking and telecommunication systems, as well as on-board clocking of OC-3, OC-12 and OC-48 speed communication systems. The MC100ES6226 can be operated from a 3.3 V or 2.5 V positive supply without the requirement of a negative supply line. Each of the output banks of three differential clock output pairs may be independently configured to distribute the input frequency or half of the input frequency. The FSEL0 and FSEL1 clock frequency selects are asynchronous control inputs. Any changes of the control inputs require a MR pulse for resynchronization of the ÷2 outputs.

MC100ES6226 - Block Diagram
MC100ES6226 - Pinout
MC100ES6226 - Block Diagram
MC100ES6226 - Pinout
  • Fully differential architecture from input to all outputs
  • SiGe technology supports near-zero output skew
  • Selectable 1:1 or 1:2 frequency outputs
  • LVPECL compatible differential clock inputs and outputs
  • LVCMOS compatible control inputs
  • Single 3.3 V or 2.5 V supply
  • Max. 35 ps maximum output skew (within output bank)
  • Max. 50 ps maximum device skew
  • Supports DC operation and up to 3 GHz (typ.) clock signals
  • Synchronous output enable eliminating output runt pulse generation and metastability
  • Standard 32-lead LQFP package
  • Industrial temperature range
  • 32-lead Pb-free package available

Documentation

Design & Development

ECAD Models

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Product Options

    Processing table
    Pkg. Type
    Lead Count (#)
    Temp. Grade
    Pb (Lead) Free
    Carrier Type
    Buy / Sample
    Part Number
    MC100ES6226AC
    circleObsolete
    memory
    view_in_ar
    		TQFP 32 C Yes Tray
    MC100ES6226ACR2
    circleObsolete
    memory
    view_in_ar
    		TQFP 32 C Yes Reel
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