Overview

The IDT5T915 2.5V differential (DDR) clock buffer is a user-selectable single-ended or differential input to five differential outputs built on advanced metal CMOS technology. The differential clock buffer fanout from a single or differential input to five differential or single-ended outputs reduces loading on the preceding driver and provides an efficient clock distribution network. The IDT5T915 can act as a translator from a differential HSTL, eHSTL, 1.8V/2.5V LVTTL, LVEPECL, or single-ended 1.8V/2.5V LVTTL input to HSTL, eHSTL, 1.8V/2.5V LVTTL outputs. Selectable interface is controlled by 3-level input signals that may be hard-wired to appropriate high-mid-low levels. The IDT5T915 true or complementary outputs can be asynchronously enabled/disabled. Multiple power and grounds reduce noise.
5T915 - Block Diagram
5T915 - Pinout
5T915 - Block Diagram
5T915 - Pinout
  • Guaranteed Low Skew 60ps (max)
  • Very low duty cycle distortion 300ps (max)
  • High speed propagation delay 2ns (max)
  • Up to 250MHz operation
  • Very low CMOS power levels
  • Hot insertable and over-voltage tolerant inputs
  • 3-level inputs for selectable interface
  • Selectable HSTL, eHSTL, 1.8V / 2.5V LVTTL, or LVEPECL input interface
  • Selectable differential or single-ended inputs and five differential outputs
  • 2.5V VDD
  • Available in TSSOP package

Documentation

Design & Development

ECAD Models

Schematic symbols, PCB footprints, and 3D CAD models from SamacSys can be found by clicking on products in the Product Options table. If a symbol or model isn't available, it can be requested directly from the website.

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Product Options

    Processing table
    Pkg. Type
    Lead Count (#)
    Temp. Grade
    Pb (Lead) Free
    Carrier Type
    Buy / Sample
    Part Number
    5T915PAGI
    circleObsolete
    memory
    view_in_ar
    		TSSOP 48 I Yes Tube
    5T915PAGI8
    circleObsolete
    memory
    view_in_ar
    		TSSOP 48 I Yes Reel
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