Overview

Description

The 9DB401 follows the Intel DB400 Differential Buffer Specification v2.0. This buffer provides four PCI-Express SRC clocks. The 9DB401 is driven by a differential input pair from a CK409/CK410/CK410M main clock generator, such as the 952601, 954101 or 954201. It provides outputs meeting tight cycle-to-cycle jitter (50 ps) and output-to-output skew (50ps) requirements.

Features

  • 4- 0.7 V HCSL differential output pairs
  • Phase jitter: PCIe Gen1 < 86 ps peak to peak
  • Supports zero delay buffer mode and fanout mode
  • Bandwidth programming available
  • 50-100 MHz operation in PLL mode
  • 50-400 MHz operation in Bypass mode

Comparison

Applications

Documentation

Design & Development

Models