The CD4076BMS types are four-bit registers consisting of D-Type flip-flops that feature three-state outputs. Data Disable inputs are provided to control the entry of data into the flip-flops. When both Data Disable inputs are low, data at the D inputs are loaded into their respective flip-flops on the next positive transition of the clock input. Output Disable inputs are also provided. When the Output Disable inputs are both low, the normal logic states of the four outputs are available to the load. The outputs are disabled independently of the clock by a high logic level at either Output Disable input and present a high impedance. The CD4076BMS is supplied in these 16-lead outline packages: Braze Seal DIP H4T, Frit Seal DIP H1E and Ceramic Flatpack H6W.
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Type | Title | Date |
Datasheet | PDF 352 KB | |
Brochure | PDF 467 KB | |
Brochure | PDF 4.85 MB | |
Price Increase Notice | PDF 360 KB | |
Other | ||
White Paper | PDF 533 KB | |
Product Advisory | PDF 499 KB | |
Product Change Notice | PDF 230 KB | |
Application Note | PDF 338 KB | |
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