25-Bit Configurable Registered Buffer for DDR2
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Overview
Description
The SSTUA32864B is a 25-Bit configurable registered buffer for DDR2 memory modules. This device is ideal for DDR2 400, 533 and 667.
Features
- 25-bit 1:1 or 14-bit 1:2 configurable registered buffer
- Supports SSTL_18 JEDEC specification on data inputs and outputs
- Supports LVCMOS switching levels on C0, C1 and RESET# inputs
- Low voltage operation
- VDD = 1.7V to 1.9V
- Available in 96 BGA package
- Drop-in replacement for ICSSSTUA32866
- Green packages available
Comparison
Applications
Documentation
= Featured Documentation
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| Type | Title | Date |
| Datasheet | PDF 569 KB | |
| End Of Life Notice | PDF 536 KB | |
| Product Change Notice | PDF 30 KB | |
| Product Change Notice | PDF 95 KB | |
| Product Change Notice | PDF 50 KB | |
| Product Change Notice | PDF 252 KB | |
| Product Change Notice | PDF 194 KB | |
| Product Change Notice | PDF 99 KB | |
| Product Change Notice | PDF 729 KB | |
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Design & Development
Models
ECAD Models
Schematic symbols, PCB footprints, and 3D CAD models from SamacSys can be found by clicking on products in the Product Options table. If a symbol or model isn't available, it can be requested directly from the website.
Processing table
| CABGA | 96 | C | Yes | Tray | ||
| CABGA | 96 | C | Yes | Reel | ||
| CABGA | 96 | C | Yes | Tray |
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