Overview

Description

Not recommended for new designs

Features

  • Low skew, low jitter PLL clock driver 
  • Feedback pins for input to output synchronization 
  • Spread Spectrum tolerant inputs 
  • With bypass mode mux 
  • Operating frequency 60 to 210 MHz 
  • Universal input (LVTTL, LVPECL, LVDS, LVCMOS)
 

Comparison

Applications

Documentation

Type Title Date
Datasheet PDF 219 KB
End Of Life Notice PDF 549 KB
End Of Life Notice PDF 545 KB
End Of Life Notice PDF 544 KB
Product Change Notice PDF 361 KB
Product Change Notice PDF 201 KB
6 items

Design & Development

Models