Overview

Description

Not recommended for new designs

Features

 

  • Higher drive than the 95V857 series devices 
  • Low skew, low jitter PLL clock driver 
  • 1 to 10 differential clock distribution (SSTL_2) 
  • Feedback pins for input to output synchronization 
  • PD# for power management 
  • Spread Spectrum-tolerant inputs 
  • Auto PD when input signal removed

Comparison

Applications

Documentation

Design & Development

Models