Overview

The 854104 is a low skew, high performance 1-to-4 Differential-to-LVDS Clock Fanout Buffer and a member of the HiPerClockS™ family of High Performance Clock Solutions from IDT. Utilizing Low Voltage Differential Signaling (LVDS), the 854104 provides a low power, low noise, solution for distributing clock signals over controlled impedances of 100?. The 854104 accepts a differential input level and translates it to LVDS output levels. Guaranteed output and part-to-part skew characteristics make the 854104 ideal for those applications demanding well defined performance and repeatability.

854104 - Block Diagram
854104 - Pinout
854104 - Block Diagram
854104 - Pinout
  • Four differential LVDS output pairs
  • One differential clock input pair
  • CLK/nCLK can accept the following differential input levels: LVPECL, LVDS, LVHSTL, HCSL, SSTL
  • Each output has an individual OE control
  • Maximum output frequency: 700MHz
  • Translates differential input signals to LVDS levels
  • Additive phase jitter, RMS: 0.232ps (typical)
  • Output skew: 50ps (maximum)
  • Part-to-part skew: 350ps (maximum)
  • Propagation delay: 1.3ns (maximum)
  • 3.3V operating supply
  • 0°C to 70°C ambient operating temperature
  • Available in lead-free (RoHS 6) packages

Documentation

Design & Development

ECAD Models

Schematic symbols, PCB footprints, and 3D CAD models from SamacSys can be found by clicking on products in the Product Options table. If a symbol or model isn't available, it can be requested directly from the website.

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Product Options

    Processing table
    Pkg. Type
    Lead Count (#)
    Temp. Grade
    Pb (Lead) Free
    Carrier Type
    Buy / Sample
    Part Number
    854104AGLF
    circleObsolete
    memory
    view_in_ar
    		TSSOP 16 C Yes Tube
    854104AGLFT
    circleObsolete
    memory
    view_in_ar
    		TSSOP 16 C Yes Reel
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