Overview

Description

This 28-bit 1:2, or 26-bit 1:2 and 4-bit 1:1, registering clock driver with parity is designed for 1.25V, 1.35V and 1.5V VDD operation

Features

  • DDR3-800/1066/1333/1600/1866/2133 rate
  • 1-to-2 Register Outputs and 1-to-4 Clock Pair Outputs support stacked DDR3 RDIMMs
  • Phase Lock Loop clock driver for buffering one differential clock pair (CK and CK) and distributing to four differential outputs
  • Supports LVCMOS switching levels on the RESET and MIRROR inputs
  • Checks priority on DIMM-independent data inputs
  • Supports dynamic 1T/3T timing transaction and output inversion feature for improved timing performance during normal operations and MRS command pass-through
  • Supports CKE Power Down operation modes
  • Supports Quad Chip Select operation features
  • RESET input disables differential input receivers, resets all registers, and disables all output drivers except ERROUT and QnCKEn
  • Provides access to internal control words for configuring the device features and adapting in different RDIMM and   system applications
  • Latch-up performance exceeds 100mA
  • ESD > 2000V per MIL-STD883, Method 3015; ESD > 200V using machine model (c = 200pF, R = 0)

Comparison

Applications

Documentation

Type Title Date
Datasheet PDF 2.42 MB
End Of Life Notice PDF 1.11 MB
Overview PDF 515 KB
Product Change Notice PDF 27 KB
Product Change Notice PDF 33 KB
5 items

Design & Development

Models