The 8SLVD2104 is a high-performance differential dual 1:4 LVDS fanout buffer. The device is designed for the fanout of high-frequency, very low additive phase-noise clock and data signals. The 8SLVD2104 is characterized to operate from a 2.5V power supply. Guaranteed output-to-output and part-to-part skew characteristics make the 8SLVD2104 ideal for those clock distribution applications demanding well-defined performance and
repeatability. Two independent buffers with four low skew outputs each are available. The integrated bias voltage generators enables easy interfacing of single-ended signals to the device inputs. The device is optimized for low power consumption and low additive phase noise.

特性

  • Two 1:4, low skew, low additive jitter LVDS fanout buffers
  • Two differential clock inputs
  • Differential pairs can accept the following differential input levels: LVDS and LVPECL
  • Maximum input clock frequency: 2GHz
  • Output bank skew: 35ps, (maximum)
  • Propagation delay: 300ps, (maximum)
  • Low additive RMS phase jitter, 156.25MHz (10kHz - 20MHz):  105fs, (maximum)
  • 2.5V supply voltage
  • Lead-free (RoHS 6) 28-Lead VFQFN package
  • -40°C to 85°C ambient operating temperature

description文档

文档标题 language 类型 文档格式 文件大小 日期
数据手册与勘误表
star 8SLVD2104 Final Data Sheet 数据手册 PDF 522 KB
应用指南 & 白皮书
AN-844 Termination - AC Coupling Clock Receivers 应用文档 PDF 170 KB
AN-846 Termination - LVDS 应用文档 PDF 133 KB
AN-842 Thermal Considerations in Package Design and Selection 应用文档 PDF 495 KB
AN-840 Jitter Specifications for Timing Signals 应用文档 PDF 442 KB
AN-833 Differential Input Self Oscillation Prevention 应用文档 PDF 180 KB
AN-834 Hot-Swap Recommendations 应用文档 PDF 153 KB
AN-836 Differential Input to Accept Single-ended Levels 应用文档 PDF 120 KB
AN-815 Understanding Jitter Units 应用文档 PDF 565 KB
AN-827 Application Relevance of Clock Jitter 应用文档 PDF 1.15 MB
AN-805 Recommended Ferrite Beads 应用文档 PDF 121 KB
PCN / PDN
PCN# : A1904-01 Add Greatek, Taiwan as an Alternate Assembly Facility 产品变更通告 PDF 983 KB
其他
RF Timing Family Product Overview 概览 PDF 331 KB
Clock Distribution Overview 概览 PDF 217 KB
IDT Clock Generation Overview 概览 PDF 1.83 MB
IDT Fanout Buffers Product Overview 产品简述 PDF 739 KB
High-Performance, Low-Phase Noise Clocks Buffers product brief 产品简述 PDF 378 KB

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