概要

説明

The M2006-02 is a VCSO (Voltage Controlled SAW Oscillator) based clock generator PLL designed for clock frequency translation and jitter attenuation. The device supports both forward and inverse FEC (Forward Error Correction) clock multiplication ratios, pin-selected from pre-programming look-up tables.

特長

  • Pin-selectable PLL divider ratios support forward and inverse FEC ratio translation, including:
  • 255/238 (OTU1) Mapping and 238/255 De-mapping
  • 255/237 (OTU2) Mapping and 237/255 De-mapping
  • 255/236 (OTU3) Mapping and 236/255 De-mapping
  • Supports input reference and VCSO frequencies up to 700MHz, supports loop timing modes (Specify VCSO frequency at time of order)
  • Low phase jitter
  • Supports active switching between inverse-FEC and non-FEC clock ratios (same VCSO center frequency)
  • Ideal for complex ratio FEC ratio translation* and for use with an unstable reference** (i.e., similar to the M2006-12 - and pin-compatible - but without the Hitless Switching and Phase Build-out functions)
  • Commercial and Industrial temperature grades
  • Single 3.3V power supply
  • Small 9 x 9 mm SMT (surface mount) package
  • Pb-free / Compliant to EC RoHS Directive (RoHS 6/6)

製品比較

アプリケーション

ドキュメント

分類 タイトル 日付
製品変更通知 PDF 361 KB
EOL通知 PDF 71 KB
2 items

設計・開発

モデル