Hello, my name is Don LaFontaine. I'm a senior principal application engineer in the analog mixed signal product group with Intersil with the focus on precision amplifiers.
In today's accelerated design cycles, it's more important than ever that we provide you with accurate SPICE models during comprehensive circuit simulations. Early SPICE models didn't always deliver the level of accuracy you needed because we had to reduce the number of nonlinear elements to minimize simulation time. Today's models can increase the number of nonlinear elements and improve the accuracy of the models. But we've done much more than that. In order to simulate the ultra low noise, high precision, and extremely low power performance characteristics, we had to radically improve the architecture of our SPICE models. The SPICE models available in our datasheets now provides you an unprecedented level of accuracy that will allow you to see how well the amplifier will perform in your design.
Today, we're going to focus on SPICE models for the ISL28127. The ISL28127 is a single-pole 10MHz amplifier. This amplifier is the first of its kind in Intersil's high-voltage PR40 precision process. The model enables the user to simulate important AC and DC parameters of the amplifier. AC parameters incorporate into the model are 1/f in flat band noise, slew rate, common mode ejection ratio, gain and phase. The DC parameters are VOS, IOS, Total Supply Current, Output Short Circuit Current Limit, and Output Voltage Swing.
The key to an accurate model is the input stage. The closer you model the input stage to the actual amplifier, the better your results. With only a few of the process parameters of the input stage transistors or MOSFETs, you can achieve very accurate AC representation of the amplifier's performance. Another advantage of this model's architecture is the ability to model amplifiers with split supplies. There is no ground reference in any of the signal processing blocks. Instead, after the differential to single-ended conversion, all internally generated node voltages are referenced to the midpoint of the supplies much like an actual amplifier.
Here is the actual schematic for the ISL28127 SPICE model. Notice from this schematic that the circuitry resembling an amplifier is only the input stage. All of the stages process the input signal with voltage control current sources, voltage control voltage sources, along with diodes, DC supply, simple resistors, capacitors, and inductors. The model's architecture process this signal through eight different blocks. We'll discuss the functionality and design considerations for each block.
The first stage in the model, moving from left to right, is the voltage noise stage. This stage generates 1/f flat band noise. To generate a flat band noise voltage of a precision amplifier with only 4nV/√Hz, all diodes and transistor model parameters for flicker noise and flicker noise exponents were set to zero and one respectively. To lower the noise for the model to single digit nanovolts, the network's Johnson noise needs to be reduced by reducing the resistor values in the model where possible. The 1/f in flat band noise of the model was achieved by adjusting DN, R17, and V5.
The next stage is the input stage. The ISL28127 was selected for this discussion to illustrate the level of accuracy obtainable by modeling the amplifier's exact input structure. The input stage of the ISL28127 consists of five bipolar transistors that model the actual device. The input stage includes a current supply to model IOS, a voltage supply to model VOS, and a voltage control voltage source along with R1 and R2 to account for CMRR of the device.
The purpose of the first gain stage is a set to combine gain of the input stage and the first gain stage to one. Setting the combined gains to one simplifies the calculation to determine the slew-rate limiting components in the second gain stage. The second gain stage is where the AVOL, bandwidth, and slew-rate of the amplifiers are set using G3, G4, R7 and 8, C2, and C3. Diodes, D4 and D5, along with DC supplies, V3 and V4, are used to set the maximum output voltage swing.
The mid-supply reference stage is simply two resistors, R9 and R10. These resistors generate a mid-supply reference voltage. The resistor values are set to one ohm to reduce the Johnson noise of the model. The high current that flows through these resistors is transparent to the model user because of the supply oscillation stage. The common mode stage consists of two voltage control current sources that drive two equal resistors in series with an inductor connected to the supply rails. The inductor simulate the typical fall off of CMRR that most amplifiers exhibit as the input frequency is increased.
The next stage is the isolation stage and it consists of two voltage control voltage sources and a current source. This stage enables the user to program the total supply current of the amplifier with just one entry into the node list. It also isolates the internal supply currents from the external supply currents seen by the user. This enables the model to provide the correct supply currents for low power amplifiers with low voltage noise.
The operation of the output stage is not entirely obvious. The amplifier's output signal after receiving all the appropriate frequency shaping appears as a voltage reference to mid-supply at the inputs of G7 and G8. G7 and G8 drive two equal resistors connected to the supply rails and act as an active current generator providing the desired output voltage drop across the resistors.
When there's no load on the output, the model draws no current from either supply thus behaving like an amplifier's output. When a load is applied to the output, equal currents will be pulled from both supply rails to make it appear as if a real amplifier. G9 and G10 force the appropriate amounts of current to make it appear as if all the current are being sourced or sunk from the correct supply. The output short circuit protection is provided by diodes, D6 and D7, along with DC supplies, V5 and V6. The output short circuit current limit is determined by adjusting the value of V5 and V6.
Now that we've shown you how we've constructed this model, let's look at the performance and compare simulation results versus actual characterization results. Simulation of input noise matches the 1/f noise at the 0.1Hz. A simulated flat band noise is about 2nV higher. A close loop gain versus frequency is line and line for graphs of 1000, 100 and 1. The model gains of 10 show the effects of the second pull largely equal to 10K and RF equal to 100K. The transient response is line on line and verifies the 3.6V/ms slew rate.
For additional characterization vs. simulation results and the model's net list, reference the ISL28127 datasheet.