RZ/A1LC is the most cost-effective part in the RZ/A1 family with an Arm® Cortex®-A9 core running at 400MHz and 2MB of on-chip SRAM to support frame-buffers on-chip.
With 2MB on-chip SRAM and a 400MHz Arm® Cortex®-A9 core, the RZ/A1LC is a great replacement for MCU designs that are trying to achieve MPU levels of performance. RZ/A1LC enables very compact embedded designs without the need to worry about memory procurement and memory EOL. Enabled for support with Linux, RTOS or Bare-metal, this is the ideal device for designing Intelligent IoT End Point devices with compactness and high performance. Supported in a 176 pin BGA package with SDRAM interface to expand up to 128MB of external memory.
|Part name / use / package||176-pin||R7S721034VCBG|
|Industry usage etc.|
|176-pin BGA (8 mm × 8 mm)
|Power supply voltage||3.3 V/1.18 V|
|Maximum operating frequency||400 MHz|
|CPU core||Arm® Cortex®-A9 (with Jazelle® and NEON™)|
|On-chip RAM||Large-capacity memory: 2 MB|
|(For video display/work area; 128 KB are shared with data retention)|
||Primary cache memory: 64 KB (separated 32K instruction/32K data, TLB128 entry) Secondary cache memory: 128 KB (with CoreLink™ Level 2 Cache Controller L2C-310)|
|External memory||Bus clock: up to 66.67 MHz|
|Direct connection to SRAM, byte select SRAM, SDRAM, and burst ROM (clock synchronous/clock asynchronous) using bus state controller.
Address/data multiplexer I/O (MPX) interface supported.
|Address space: 64 MB × 6|
|Data bus width: external 8/16/32 bits|
|Graphics functions||Video display controller (1 channel of video input and 1 channel of panel output)|
|Capture engine unit (CMOS camera interface)|
|Audio||SCUX (with built-in asynchronous sampling rate conversion, digital volume & mute, and mixer function)|
|Serial sound interface × 4 channels|
|Renesas SPDIF interface|
|Timers||Multifunction 16-bit timer (MTU2) × 5 channels|
|32-bit OS timer × 2 channels|
|Connectivity functions||USB 2.0 host/function module × 2 channels (host or function selectable)|
|SD host interface × 2 channels (must obtain SD card license)|
|MMC host interface|
|Ethernet controller (10 Mbps/100 Mbps transfer, IEEE802.3 PHY interface MII)|
|SPI multi-I/O bus controller x 1 channel (up to 2 serial flash memory connectable to 1 channel, direct execution from CPU supported)|
|Serial communication interface with 16-stage FIFO (SCIF) × 5 channels (asynchronous and clock synchronous serial communication possible)|
|Serial communication interface × 2 channels (smart card interface, IrDA 1.0)|
|Renesas serial peripheral interface × 3 channels|
|I2C bus interface x 4 channel|
|Controller area network (CAN) × 2 channels|
|System analog functions||Clock pulse generator (CPG): built-in PLL, maximum 32 times multiplication, built-in SSCG circuit|
|Direct memory access controller × 16 channels|
|Interrupt controller (with Arm® Generic Interrupt Controller [PL390])|
|A/D converter (12-bit resolution) × 8 channels|
|JTAG standard pin layout|
|Boot modes||Boot mode 0: Boot from memory connected to CS0 space (16-bit bus)|
|Boot mode 1: Boot from serial flash memory|
|Boot mode 2: Boot from built-in NAND flash memory of SD controller|
|Boot mode 3: Boot from built-in NAND flash memory of MMC controller|
|Power-down modes||Sleep mode|
|Software standby mode|
|Deep standby mode|
|Module standby mode|
*Arm, Cortex, CoreLink, and CoreSight are registered trademarks or trademarks of Arm Limited.
CAN (Controller Area Network): An automotive network specification developed by Robert Bosch GmbH of Germany.
All other names of products or services mentioned here are trademarks or registered trademarks of their respective owners.
You can find an explanation of orderable part numbers here.
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Hardware Design Support
|Oscillation circuit characteristics
Please search for your resonator on its manufacturer's site linked below. If you require optimal oscillation circuit constants for your particular system, please ask the manufacturer of the oscillator.
For main clock resonators:
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