Low skew, low jitter PLL clock driver; 1 to 5 differential clock distribution (SSTL_18)
Features
- Feedback pins for input to output synchronization
- Spread Spectrum tolerant inputs
- Auto PD when input signal is at a certain logic state
Low skew, low jitter PLL clock driver; 1 to 5 differential clock distribution (SSTL_18)
| Title | Other Languages | Type | Format | File Size | Date | |
|---|---|---|---|---|---|---|
| Datasheets & Errata | ||||||
| 97ULP845A Datasheet | – | Datasheet | 329 KB | |||
| PCNs & PDNs | ||||||
| PDN# : CQ-14-02R2 | – | Product Discontinuation Notice | 549 KB | |||
| PDN# : CQ-14-02R1 PRODUCT DISCONTINUANCE NOTICE | – | Product Discontinuation Notice | 545 KB | |||
| PDN# : CQ-14-02 PRODUCT DISCONTINUANCE NOTICE | – | Product Discontinuation Notice | 544 KB | |||
| PCN#: A1309-03 Additional Assembly Sources | – | Product Change Notice | 398 KB | |||