Overview

Description

The RC32012A regenerates and distributes ultra-low jitter clock outputs and features up to 4 independent frequency domains that can be either locked to the external reference clock or locked to a free-run crystal or oscillator. Digital PLLs (DPLLs) support hitless reference switching between references from redundant timing sources. The device supports multiple independent timing channels for: IEEE 1588 clock synthesis; SyncE clock generation; jitter attenuation and radio clock generation including SYSREF generation for converters. Input-to-input, input-to-output and output-to-output phase skew can all be precisely managed.  The device outputs ultra-low-jitter clocks that can directly synchronize SERDES running at up to 56Gbps; as well as CPRI/OBSAI, SONET/SDH ADC/DAC. The device is ideal for use in 100G/200G/400G/800G telecom switch line cards, fabric cards and wireless small cell applications. 

To see other devices in this product family, visit the ClockMatrix Timing Solutions page.

Features

  • Two timing channels and four independent frequency domains
  • Output jitter below 100fs RMS
  • Digital PLLs (DPLLs) lock to any frequency from 0.5kHz to 1GHz
  • DPLLs / Digitally Controlled Oscillators (DCOs) generate any frequency from 0.5Hz to 1GHz
  • DCO outputs can be aligned in phase and frequency with the outputs of any DPLL or DCO
  • Can be used as a jitter attenuator, clock generator, or synchronizer
  • Reference monitors qualify/disqualify references depending on LOS, activity, frequency monitoring and/or LOS input pins
  • Automatic reference selection state machines select the active reference for each DPLL based on the reference monitors, priority tables, revertive / non-revertive and other programmable settings
  • Device requires a crystal oscillator or fundamental-mode crystal: 25MHz to 54MHz
  • The device can configure itself automatically after reset via:
    • Internal Customer-programmable One-Time Programmable memory 
    • Standard external I2C EPROM via separate I2C Master Port

Applications

Documentation

Title Type Date
PDF2.33 MB
Datasheet
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Application Note
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Application Note
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Datasheet
PDF2.93 MB
Guide
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Guide
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Guide
XLSX394 KB
Other
PDF320 KB
Overview
PDF1.83 MB
Overview
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Product Change Notice
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Product Change Notice
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Product Change Notice
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Schematic

Design & Development

Software & Tools

Software Downloads

Title Type Date
ZIP50.80 MB
Software & Tools - Other
GZ538 KB
Software & Tools - Other
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Software & Tools - Other
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Software & Tools - Other

Boards & Kits

Boards & Kits

Models

Models

Title Type Date
ZIP2 KB
Model - BSDL
ZIP2.55 MB
Model - IBIS

Support

Videos & Training

IDT ClockMatrix™ Timing Solution for 100Gbps Interface Speeds (IEEE 1588, OTN, and SyncE)

Introducing the IDT ClockMatrix™ family of devices - high-performance, precision timing solutions designed to simplify clock designs for applications with up to 100 Gbps interface speeds. 

They can be used anywhere in a system to perform critical timing functions, such as clock generation, frequency translation, jitter attenuation and phase alignment. A range of devices in the family support BBU, OTN, SyncE, synthesizer and jitter attenuator applications with several density options for each.

For more information, visit www.idt.com/clockmatrix.

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