The 553S is a low skew, single input to four output, LVCMOS clock buffer. The 553S has best in class additive phase Jitter of sub 50 fsec.
 

Features

  • Low additive phase jitter RMS: 50 fs
  • Extremely low skew outputs (50 ps)
  • Low cost clock buffer
  • Packaged in 8-pin SOIC and small 8-pin DFN package, Pb-free
  • Input / Output clock frequency up to 200 MHz
  • Ideal for networking clocks
  • Operating Voltages: 1.8 V to 3.3 V
  • Output Enable mode tri-states outputs
  • Advanced, low power CMOS process
  • Extended temperature range (-40°C to +105°C)

Product Options

Orderable Part ID Part Status Pkg. Type Lead Count (#) Temp. Grade Pb (Lead) Free Carrier Type Buy Sample
553SCMGI
Active COL 8 I Yes Cut Tape
Availability
553SCMGI8
Active COL 8 I Yes Reel
Availability
553SDCGI
Active SOIC 8 I Yes Tube
Availability
553SDCGI8
Active SOIC 8 I Yes Reel
Availability

Documentation & Downloads

Title Other Languages Type Format File Size Date
Datasheets & Errata
553S Datasheet Datasheet PDF 249 KB
Application Notes & White Papers
AN-845 Termination - LVCMOS Application Note PDF 146 KB
AN-842 Thermal Considerations in Package Design and Selection Application Note PDF 495 KB
AN-840 Jitter Specifications for Timing Signals Application Note PDF 442 KB
AN-815 Understanding Jitter Units Application Note PDF 565 KB
PCNs & PDNs
PCN# : A1905-02 Adding Carsem, Malaysia as Alternate Assembly Location & Change Material Sets Product Change Notice PDF 268 KB
PCN# : A1602-01(R1) Add Greatek Taiwan as Alternate Assembly Product Change Notice PDF 611 KB
PCN# : A1602-01 Add Greatek Taiwan as Alternate Assembly Product Change Notice PDF 611 KB
Downloads
553S IBIS Model Model - IBIS ZIP 26 KB
Other
Clock Distribution Overview 日本語 Overview PDF 217 KB
Timing Solutions Products Overview Overview PDF 4.11 MB
IDT Clock Generation Overview 日本語 Overview PDF 1.83 MB