PCIe clock distribution devices (buffers) are usually required in all but the smallest PCIe systems. Device pin-count limitations restrict the number of PCIe clocks than can be generated in a single device. Sometimes, board routing constraints (the proverbial “rat’s nest”) also limit the number of clocks that can be distributed from a single area. Fan out buffers allow a single clock to be routed from a congested board area to the section needing multiple copies, where the buffer then fans out the clock locally. Sometimes, the designer only has a single PCIe clock coming from a connector and needs multiple copies. Again, fan out buffers solve the problem.

Renesas PCIe buffers range from 2 to 19 outputs, and address PCI Express Gen 1, Gen 2, Gen 3, Gen 4 and Gen 5 requirements. Additionally, Renesas offers PCIe buffers both with and without a PLL inside. The PLL creates a zero-delay buffer, eliminating propagation delay through the device, which reduces transport delay. Renesas PLL-based PCIe buffers have a strap pin to select the PLL BW, allowing cascading without overlapped jitter peaking. The Renesas PLL-based PCIe buffers also have either a strapping pin, or an SMBus bit that bypasses the PLL. This converts the PLL-buffer into a pure fan out buffer (no PLL). If the target system uses spread spectrum, a pure fan out buffer is needed 98% of the time. Renesas also offers pure PCIe fan out buffers without a PLL. These non-PLL based devices feature reduced propagation delay compared with a PLL-based device because they eliminate the bypass mux found in the PLL-based parts.

PCI Express Timing Solutions Overview (PDF)